Latest news with #DVCon
Yahoo
3 days ago
- Business
- Yahoo
DVCon U.S. 2026 Announces Call for Extended Abstracts, Workshop and Tutorial Proposals
Submit proposals by September 7, 2025, to help drive innovation in design and verification GAINESVILLE, Fla., June 03, 2025 (GLOBE NEWSWIRE) -- The 2026 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, is pleased to announce its Call for Extended Abstract, Workshop, and Tutorial Proposals. The 38th annual DVCon U.S. will be held March 2-5 at the Hyatt Regency Hotel, Santa Clara, CA. 'DVCon U.S. continues to be the premier venue for exploring the latest trends, technologies, and standards in design and verification,' stated Xiaolin Chen, DVCon U.S. 2026 General Chair. 'We invite proposals that share real-world experiences, innovative methodologies, and forward-looking insights. Our goal is to deliver an exceptional technical program while preserving the personal connections and collaborative spirit that have long defined the DVCon experience.' Extended Abstract Information DVCon U.S. 2026 invites engineers, researchers, and practitioners to submit extended abstracts that provide deep technical insights, practical case studies, and innovative approaches across the design and verification landscape. Submissions should focus on real-world experiences and address emerging trends that are shaping the future of electronic system development. Suggested topic areas include, but are not limited to: Functional verification and validation Safety-critical design and verification Low-power design techniques Machine learning and big data applications Design and verification reuse and automation Mixed-signal design and verification Authors may also incorporate topics such as EDA tool usage, FPGA-based design, specialized verification languages (e.g., SVA or PSL), scripting, Portable Stimulus applications, AMS techniques, and IoT-related methodologies. Extended abstracts should be between 600 and 1,200 words and demonstrate technical depth, innovation, and relevance. More information and guidelines for DVCon U.S. 2026 abstract submissions can be found here. Sponsored Short Workshop and Tutorial Information DVCon U.S. 2026 welcomes proposals for technical tutorials and short workshops that offer high-impact educational content for design and verification professionals. These sessions provide an excellent opportunity for industry experts to share knowledge, demonstrate tools and methodologies, and engage directly with attendees. Short workshops are 90-minute sponsored sessions open to all attendees registered for the full conference. Scheduled for both Monday and Thursday, these workshops may be formatted as hands-on demonstrations or lecture-style presentations, allowing flexibility in delivery and engagement. DVCon U.S. technical tutorials are three-hour sessions included with full conference registration. The Technical Program Committee seeks proposals that are timely, highly relevant, and rich in continuing education value. Topics should address current challenges and trends in design and verification. Suggested topics for both workshops and tutorials include: SystemVerilog for design and verification SystemC, C, and C++ in system-level design Software-driven and SoC verification Assertion-based verification (SystemVerilog, PSL) Coverage-driven verification and debug techniques Low-power design strategies and high-level synthesis Mixed-signal modeling and AMS verification Secure IP-based SoC design and encryption Transaction-level modeling, ESL design, and IP integration (IP-XACT) Portable Stimulus and standards adoption Formal methods, emulation, FPGA prototyping, and post-silicon debug Embedded software co-verification and productivity methods Functional safety, security, and open-source methodologies Machine learning applications in design and verification Proposals should include an abstract between two to five paragraphs (not exceeding 1,000 words) that clearly outline the objective, technical depth, and value to attendees. For more details on DVCon U.S. 2026 workshop and tutorial proposal guidelines, including pricing, visit here. Submission DeadlineThe submission site for all proposals opens July 15. The deadline to submit extended abstracts, tutorial and workshop proposals is September 7, 2025. For inspiration and to view proceedings from past conferences, visit the archives site. About DVConDVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit For more information about DVCon U.S., please visit here. Follow DVCon on Facebook, LinkedIn or @dvcon_us on X or to comment, please use #dvcon_us. For more information, please contact: Laura LeBlanc Barbara Benjamin Conference Catalysts, LLC HighPointe Communications 352-872-5544 Ext. 115 503-209-2323 lleblanc@ barbara@
Yahoo
11-03-2025
- Business
- Yahoo
DVCon U.S. 2025 Announces Stuart Sutherland Best Oral Presentation & Best Poster Winners, Record Attendance & Conference Highlights
Change in venue to Hyatt Regency, Santa Clara, California for DVCon U.S. 2026 GAINESVILLE, Fla., March 11, 2025 (GLOBE NEWSWIRE) -- The 2025 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative (Accellera), concluded its 37th annual event in San Jose, CA earlier this month with record attendance since returning to an in-person event. The 2025 Stuart Sutherland Best Oral Presentation and Best Poster winners, as voted on by attendees, were announced during a reception in the exhibit hall on February 26. Participants from 32 countries, representing approximately 350 companies, attended DVCon U.S. 2025, including 404 first-time attendees. The event featured 32 sponsors and exhibitors, six of whom were making their debut. Overall attendance reached approximately 1,067, including representatives from 26 exhibiting companies. The exhibit floor was sold out. "DVCon U.S. 2025 was a tremendous success, bringing together the brightest minds in design and verification to explore the latest advancements in AI, formal verification, and industry standards,' stated Tom Fitzpatrick, DVCon U.S. 2025 General Chair. 'With attendance reaching a new record since returning in-person, the enthusiasm and engagement from our attendees, speakers, and exhibitors showcased the vibrant innovation driving our industry forward. From thought-provoking keynotes to informative and educational technical sessions and a dynamic exhibition floor, this year's conference reaffirmed DVCon's role as the premier event for the design and verification community. We're excited to be moving to a new venue in 2026, giving the conference room to grow and continue delivering an exceptional experience for our community." The first-place award for the Stuart Sutherland Best Oral Presentation, as voted by conference attendees, was presented to Pritam Roy, Ping Yeung, Joon Hong, Abhishek Desai, Aishwarya Raj, Chirag Agarwal, and Dhruvin Patel from NVIDIA for their presentation, 'Hierarchical Formal Verification and Progress Checking of Network-on-Chip Design.' Second-place honors went to Aman Kumar, Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna, and Djones Lettnin from Infineon Technologies for their presentation, 'Saarthi: The First AI Formal Verification Engineer.' Third place was awarded to Sam Mellor from Arm for 'User Programmable Targeted UVM Debug Verbosity Escalation.' Top honors for Best Poster went to Jonathan Bonsor-Matthews from LightBlue Logic Limited and Greg Law from Undo Limited for their poster, 'Time-Travel Debugging for High-Level Synthesis Code.' Sean Little from Verus Research took second place for 'A Survey of Predictor Implementation Using High-Level Language Co-Simulation.' Third place was awarded to Ahmed Allam from ICpedia for 'Register Access by Intent: Towards Generative RAL-Based Algorithms.' Highlights of the Week: The industry keynote on Tuesday, 'AI Factories Drive Re-invention of Chip Design, Verification and Optimization,' was presented by Ravi Subramanian, Chief Product Management Officer at Synopsys and his guest, Artour Levin, Vice President of AI Silicon Engineering at Microsoft Corporation. The two discussed the challenges in the industry and opportunities for advancement. Subramanian declared, 'We are at the dawn of the next industrial revolution. AI factories will define the landscape for the next decades, if not centuries.' Wednesday morning kicked off with an insightful panel discussion: "Are AI Chips Harder to Verify?' Verification experts from across the industry explored the unique challenges of verifying AI-driven silicon. Panelists shared perspectives on how different business models impact verification strategies and emphasized the need for early stakeholder involvement when integrating AI into chip development. Most experts agreed that AI chips are 50% more difficult to verify due to their complexity and dynamic behaviors. However, they cautioned that AI is just one part of the solution to the industry's evolving challenges. On Wednesday afternoon, Vivek Prasad, Vice President of Design Engineering EcoSystem Enablement, at Natcast, presented the invited keynote, 'The Role of EDA in U.S. Economic Security.' His talk looked at the history of EDA and how it has enabled the semiconductor revolution, where it currently faces challenges, and how CHIPS for America and its CHIPS National Advanced Packaging Manufacturing Program is helping to address those challenges going forward. The highly anticipated Poster Ninja Warrior Session once again highlighted the best in technical innovation, culminating in the selection of the Best Poster Award winners. For the third consecutive year, the top four poster presenters went head-to-head in a dynamic showdown, delivering their presentations in front of an engaged audience. Fielding questions from a panel of judges, the session was an exciting competition among colleagues. Save the date: DVCon U.S. 2026 will be held March 2-5 at the Hyatt Regency in Santa Clara, California. Xiaolin Chen is General Chair for DVCon U.S. 2026. The proceedings from DVCon U.S. 2025 will be available to the public in June. To view proceedings from past conferences, visit the archives site. About DVConDVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit For more information about DVCon U.S., visit the DVCon U.S. website. Follow DVCon U.S. on Facebook, LinkedIn or X. For more information, please contact: Laura LeBlanc Barbara Benjamin Conference Catalysts, LLC HighPointe Communications 352-872-5544 Ext. 115 503-209-2323 lleblanc@ barbara@
Associated Press
20-02-2025
- Business
- Associated Press
Advantest Introduces SiConic: Groundbreaking Solution for Automated Silicon Validation
TOKYO, Feb. 20, 2025 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) today unveiled SiConic: a scalable solution for automated silicon validation. Designed to address the increasing complexity of advanced systems-on-chip (SoCs), SiConic enables design verification (DV) and silicon validation (SV) engineers to achieve faster sign-off with unparalleled reliability, efficiency and collaboration. Debuting next week at DVCon in San Jose, Calif., SiConic signals Advantest's commitment to transforming the R&D process for its customers. The semiconductor industry is facing unprecedented challenges. Growing SoC design complexity, together with the adoption of 3D packaging and heterogeneous integration, is straining traditional validation workflows. DV and SV teams are under pressure to reduce time-to-market and time-to-quality – even as more devices with more intricate features are being developed within constrictive timelines. Reusing the wealth of verification content developed in pre-silicon would provide an efficiency and quality breakthrough. However, the industry lacks the automated flow and tools to reliably re-use and extend verification tests for silicon validation. SiConic's ecosystem – including EDA partners such as Cadence, Siemens and Synopsys – overcomes this barrier to reuse, enabling engineering efficiency and accelerated test execution on real silicon. SiConic Explorer, the platform's software backbone, offers an automated flow by integrating seamlessly with EDA verification tools based on the Accellera Portable Test and Stimulus Standard (PSS), e.g., the Cadence Perspec System Verifier. In addition, integration with debuggers, such as Lauterbach's TRACE32 debugging tool, accelerates the bring-up of complex multi-IP test cases. SiConic Link is the hardware foundation of the SiConic solution on a bench. With its high-speed I/O (HSIO) capability, SiConic Link supports protocols such as PCIe and USB to enable functional validation with high throughput and rich tracing capabilities during test execution. The test instrument provides control interfaces (e.g., JTAG, SPI) and general-purpose I/Os, improves the debugging workflow and provides extensive control and observability of the device in its target board environment. With SiConic, DV engineers can now leverage familiar pre-silicon techniques, expanding their functional coverage in post-silicon. Similarly, SV engineers benefit from seamless load, set parameters and debug of PSS-based or manually directed content on silicon, thereby enabling rapid and reliable device bring-up and functional characterization. The highly portable solution can be easily scaled for use by distributed global R&D teams collaborating on a complex SoC with diverse IP blocks. SiConic enables confident sign-off decisions through team collaboration and data-driven insights – building trust with customers receiving early samples and expecting reliable ramp and operation during the lifetime of their systems. Industry Support Leading Advantest IC customers and EDA partners are already working with SiConic and seeing the benefits of its performance and productivity advantages. 'With the shift toward increasingly complex multi-chiplet designs, the challenge of pre-silicon verification and post-silicon validation requires new techniques and approaches to ensure quality and performance,' said Alex Starr, AMD Corporate Fellow. 'AMD is delighted that our collaboration on SiConic, particularly focusing on PSS, offers an integrated path to bridge pre- and post-silicon worlds with streamlined, scalable and comprehensive test content.' 'The scaling of AI and mission-critical end applications such as automotive ADAS brings escalating complexity and quality challenges that require new solutions,' said Paul Cunningham, senior vice president and general manager, System Verification Group, Cadence Design Systems. 'Cadence is leading in verification solutions with state-of-the-art, top-level verification by our Perspec System Verifier, based on PSS. We're excited to partner with Advantest to extend our solutions onto silicon – leveraging PSS content to silicon, with the controllability and observability of SiConic, will enable joint customers to reach unprecedented coverage and deep insights into challenging designs.' 'Over decades, our industry has been challenged by test content that requires intense debugging and cross-team collaboration for bring-up on silicon and drawing conclusions in diverse bench and ATE environments. Given today's device complexity and quality demands, we need a breakthrough in efficiency enabled by a systematic and automated flow,' stated Juergen Serrer, chief technology officer and executive vice president, SoC Test Business Unit, Advantest. 'The engineers developing tests in pre-silicon need a unified environment to directly load, debug and gain insights on silicon. SiConic is Advantest's answer to this challenge. We are committed to extending SiConic across all major test types and applications in collaboration with industry-leading customers and partners.' At DVCon, February 24-27 Advantest will present details about SiConic on February 24 at 1:30 p.m. during a tutorial hosted by Cadence. On February 25 at 3:00 p.m., Advantest will present a paper with Qualcomm and Cadence called 'Accelerating Device Sign-off through a Unified Environment for Design Verification, Silicon Validation, and ATE with PSS.' For more information about SiConic and Advantest's full ATE portfolio, you can find it in booth 107 at DVCon. About Advantest Corporation Advantest (TSE: 6857) is the leading manufacturer of automatic test and measurement equipment used in the design and production of semiconductors for applications including 5G communications, the Internet of Things (IoT), autonomous vehicles, high-performance computing (HPC) including artificial intelligence (AI) and machine learning, and more. Its leading-edge systems and products are integrated into the most advanced semiconductor production lines in the world. The company also conducts R&D to address emerging testing challenges and applications; develops advanced test-interface solutions for wafer sort and final test; produces scanning electron microscopes essential to photomask manufacturing; and offers system-level test solutions and other test-related accessories. Founded in Tokyo in 1954, Advantest is a global company with facilities around the world and an international commitment to sustainable practices and social responsibility. More information is available at . 3061 Zanker Road
