Latest news with #EMIB-T
Business Insider
3 days ago
- Business
- Business Insider
'Data Center GPUs' Prove Little Help for Intel Stock (NASDAQ:INTC)
Chip stock Intel (INTC) has been eagerly fighting to win back its presence in the data center. And as more data centers start taking on artificial intelligence (AI) operations, that has left Intel somewhat on the back foot. But Intel is working to make a comeback, and giving its Battlemage graphics processing unit (GPU) line some extra room to run. Sadly, this did little good for Intel stock, as shareholders rejected the notion and bolted for the exits, taking shares down nearly 4% in Friday afternoon's trading. Confident Investing Starts Here: Reports noted that Intel engineers are currently working on a Linux kernel to drive data center GPUs, which pretty much means Battlemage at this point. Intel already has a couple of entrants in the GPU field—the Arc B-Series and the Arc Pro B-Series—but with this new kernel being established, reports note, that will get Battlemage into the fray as well, doing more than just improving people's gaming experience. The reports suggest that the new combination will come out under the Data Center GPU Flex Series, unless some fresh power is brought in that makes it more along the lines of the Data Center GPU Max Series. Word from the patch notes, meanwhile, notes that the new data center GPU line will have access to the Synopsis DesignWare I2C host adapter, which handles connection duties for a range of microcontrollers. New Packaging, Too Further, Intel is also working to bring out new word about its packaging, including one big breakthrough in the EMIB-T class. EMIB-T, noted a report from Tom's Hardware, will offer larger-size chip packages as well as greater options in power delivery, and even an improvement in heat spreader operations for a more reliable chip overall. The EMIB-T design, meanwhile, is fairly similar to its EMIB lineup, but with the addition of 'through-silicon vias,' (TSVs) that lend access to better communications and power flow between dies and chiplets in the chip overall. That again should help improve efficiency and speeds, making chips made in this fashion more attractive overall. Is Intel a Buy, Hold or Sell? Turning to Wall Street, analysts have a Hold consensus rating on INTC stock based on one Buy, 26 Holds and four Sells assigned in the past three months, as indicated by the graphic below. After a 34.36% loss in its share price over the past year, the average INTC price target of $21.29 per share implies 8.76% upside potential.
Yahoo
30-04-2025
- Business
- Yahoo
Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
Highlights: Significantly expanded portfolio of Cadence design IP optimized for Intel's advanced technologies AI-driven digital and analog/custom EDA solutions certified for Intel 18A technology PDK, delivering optimized PPA Co-developed advanced packaging reference design flow for Intel Foundry's EMIB and EMIB-T technology certified for latest PDK Engagement underway on early design technology co-optimization for Intel 14A-E Joins the Intel Foundry Chiplet Alliance as a founding member SAN JOSE, Calif., April 29, 2025--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence® digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK). These advancements are being showcased today at Intel Foundry Direct Connect, underscoring Cadence's continued leadership in driving industry innovation for artificial intelligence and machine learning (AI/ML), high-performance computing (HPC) and advanced mobility applications through its strategic partnership with Intel Foundry. Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. With this collaboration, joint customers can achieve exceptional power, performance and area (PPA) efficiencies, accelerating time to market for cutting-edge system-on-chip (SoC) designs. The latest additions to Cadence's broad portfolio of design IP in Intel 18A/18A-P technologies are available shortly and include: 224G SerDes with long-range performance for Universal Accelerator Link™ (UALink™) and Ultra Ethernet™, the latest standards for scaling up and out accelerator networks in AI factories DDR5 – 12.8G with MRDIMM Gen2 support, supporting the latest in DRAM technology for AI applications Universal Chiplet Interconnect Express™ (UCIe™) 1.1 48G, which seamlessly facilitates multi-die system-in-package (SiP) integration for scalable chiplet architectures at high data rates Advanced computing and peripheral connectivity IP compatible with the latest consumer standards, enabling scalable embedded applications for a wide range of consumer and mobility requirements: 10G multi-protocol SerDes PHY, supporting PCI Express® (PCIe®) 3.0, DisplayPort and Ethernet eUSB2 v2.0 MIPI® SoundWire® I3S Cadence's expanded portfolio also includes a range of design IP already available in the Intel 18A technology family: 112G Extended Long-Reach SerDes with superior bit error rate (BER) performance for robust data integrity over longer distances; 64G MP PHY for PCIe 6.0, CXL 3.0 and 56G Ethernet; LPDDR5X/5 – 8533 Mbps with multi-standard support; and UCIe 1.0 16G for advanced packaging. Mutual customers now have a broad range of IP options for their AI/ML, HPC and mobility applications leveraging Intel 18A/18A-P RibbonFET and PowerVia implementation. In addition to the new IP for Intel 18A and 18A-P technologies, Cadence's comprehensive suite of AI-driven design and analog/custom design solutions has been certified for the latest Intel 18A node PDK. This includes the complete AI-driven Cadence RTL-to-GDS flow, featuring a range of robust solutions such as the Cadence Cerebrus® Intelligent Chip Explorer, Genus™ Synthesis Solution, Innovus™ Implementation System, Quantus™ Extraction Solution, Quantus Field Solver, Tempus™ Timing Solution and Pegasus™ Verification System. The flow also includes custom IC design solutions such as Cadence Virtuoso® Studio, the integrated Spectre® Platform and the Voltus™-XFi Custom Power Integrity Solution. Meanwhile, Cadence and Intel Foundry are engaging in early design technology co-optimization for Intel 14A-E to establish the readiness of Cadence EDA flows for the next-generation advanced node. In addition, Cadence and Intel Foundry have also partnered to develop an advanced packaging workflow leveraging Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology. This solution streamlines the integration of complex multi-chiplet architectures—eliminating data conversion, shortening design cycles and enabling concurrent activities with early thermal, signal integrity and power modeling. It also ensures compliance with standards, reduces risks and simplifies adoption of Intel technology. Continuing its support of the Intel Foundry Accelerator Alliance Program, Cadence has joined the Intel Foundry Chiplet Alliance Program as a founding member to ensure its solutions will help provide an assured and scalable path for customers looking to deploy designs that leverage interoperable and secure chiplet solutions for targeted applications and markets. Cadence is already a participating member in the EDA, IP, Design Services and USMAG Alliances. "Cadence is at the forefront of facilitating next-generation AI, HPC and mobility designs with Intel 18A and 18A-P technologies, and our collaboration ensures that our mutual customers can leverage our robust design IP and AI-driven digital and analog/custom solutions for unparalleled performance and efficiency," said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. "Our expanded design IP portfolio for Intel Foundry builds on our commitment to delivering best-in-class silicon solutions, and our advanced implementations of leading standards are key to achieving scalable, high-performance designs. We look forward to continuing to partner with Intel Foundry to build out IP solutions for the AI factories and compute platform needs of the future as well as today." "As we optimize solutions through our ongoing collaboration, the combination of Cadence's innovative IP solutions and Intel 18A and 18A-P technologies delivers advantages for AI/ML and HPC applications," stated Suk Lee, vice president and general manager, Ecosystem Technology Office at Intel Foundry. "Working together, we are accelerating the development of high-performance solutions, including for chiplets, that meet the evolving needs of the industry and empower our mutual customers to drive PPA efficiencies and accelerate time to market for their innovative next-generation SoC designs." For more information about Cadence and its collaboration with Intel Foundry, please visit the Intel Foundry partner webpage. About Cadence Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence's Intelligent System Design™ strategy, are essential for the world's leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world's top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at © 2025 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at are trademarks or registered trademarks of Cadence Design Systems, Inc. MIPI and SoundWire are registered trademarks owned by MIPI Alliance. PCI Express and PCIe are registered trademarks of PCI-SIG. Universal Chiplet Interconnect Express and UCIe are trademarks of UCIe Consortium. All other trademarks are the property of their respective owners. Category: Featured View source version on Contacts For more information, please contact: Cadence Newsroom408-944-7039newsroom@ Sign in to access your portfolio
Forbes
29-04-2025
- Business
- Forbes
Intel Foundry And Synopsys Collaborate To Fast-Track 18A Chip Development
Intel CEO Lip-Bu Tan On Stage At Intel Foundry Direct Connect With Synopsys President And CEO ... More Sassine Ghazi In a joint announcement reflecting the growing importance of ecosystem collaboration in semiconductor design, Synopsys and Intel Foundry have expanded their partnership in support of chip development on Intel's 18A and 18A-P process technologies. This engagement aims to streamline and scale next-generation chip design for applications in AI, HPC, data center, client PC and mobile platforms. As Intel continues to evolve its foundry strategy under the leadership of its new CEO Lip-Bu Tan, collaborations with EDA and core IP providers like Synopsys are key to enabling a competitive and accessible design infrastructure for customers targeting Intel's new advanced process nodes. At the center of the announcement is Intel's 18A chip process, which introduces RibbonFET (Intel's gate-all-around transistor design) and PowerVia (backside power delivery), among other cutting-edge semiconductor design technologies. These innovations are key enablers that improve both performance and power efficiency of chips built on Intel processes at scale. Intel's 18A-P variant builds on this by offering additional optimization for performance-critical applications, and with better transistor density as well. Synopsys Electronic Design Automation Tools And IP Solutions To Accelerate Chip Design On Intel 18A To help design teams adopt these nodes effectively, Synopsys has certified its digital and analog EDA flows for Intel 18A, and those flows are now production-ready for 18A-P. Synopsys also provides a broad library of silicon-proven IP, including chip and system interfaces and foundation IP essential for building advanced system-on-chip designs. The availability of validated tools and IP is critical for customers seeking to reduce development timelines and manage risk when targeting these advanced chip fab nodes. In addition to process design support, the partnership also includes an optimized EDA reference flow for Intel's EMIB-T (Embedded Multi-die Interconnect Bridge Technology), a 2.5D advanced chip packaging solution that facilitates high-bandwidth integration across multiple dies within a single package. The reference flow supports a unified exploration-to-signoff platform, allowing design teams to manage 2.5D and 3D multi-die architectures more efficiently. This is particularly relevant as chip and system-level integration increasingly supplements traditional semiconductor node scaling (Moore's Law) in driving performance and functionality. Intel EMIB-T 2.5D Packaging Technology For Multi-Die System On Chip Designs EMIB-T and related advanced chip packaging technologies are an Intel strong suit for next-generation designs, particularly in data center AI applications, where compute density with better memory proximity helps drive performance. A certified EDA flow can reduce the complexity associated with these packaging technologies and support greater adoption across the industry. Looking ahead, Synopsys and Intel Foundry are also working together on early design enablement for Intel's 14A-E node, which is currently in development. While technical details are still scarce, 14A-E is expected to extend the architectural and manufacturing improvements introduced with 18A with 15 to 20% better performance-per-watt characteristics. By engaging early in the development of tools, flows and IP for 14A-E, the two companies aim to ensure that design infrastructure is in place when the process becomes commercially available, currently slated for late 2026 into early 2027. This approach reflects a broader trend toward concurrent design tool process co-optimization as process chip manufacturing nodes become more complex. This collaboration is aligned with Intel Foundry's broader strategy to build a complete ecosystem of tools, IP, and packaging capabilities that lower the barrier for entry for fabless semiconductor companies, like NVIDIA, Qualcomm, AMD, Broadcom, hot chip and tech start-ups, and many others. Having production-ready flows and validated IP in place is essential for serving both internal product groups at Intel and external customers. For Synopsys, the partnership reinforces its leadership in EDA enablement at advanced nodes and its commitment to supporting emerging packaging and system-level design methodologies. As complexity rises across the design stack, the need for integrated, validated solutions will continue to grow. From a market perspective, the announcement reflects how ecosystem partnerships are becoming foundational to delivering innovation at the angstrom scale. By working in parallel across process development, packaging and design flows, Intel and Synopsys customers can mitigate risk and shorten development cycles. The expanded collaboration between Synopsys and Intel Foundry provides a structured path for design teams targeting Intel's advanced process technologies, including 18A, 18A-P, and the future 14A-E node. With certified EDA flows, a broad IP portfolio, and advanced packaging support for EMIB-T, the partnership addresses key challenges in modern chip development. It will be interesting to track how the two companies progress as new external customers adopt Intel's 18A and advanced process nodes for state-side manufacturing here in the US.
Business Wire
29-04-2025
- Business
- Business Wire
Keysight EDA and Intel Foundry Collaborate on EMIB-T Silicon Bridge Technology for Next-Generation AI and Data Center Solutions
SANTA ROSA, Calif.--(BUSINESS WIRE)-- Keysight Technologies, Inc. (NYSE: KEYS) announced today a collaboration with Intel Foundry to support Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology, a cutting-edge innovation aimed at improving high-performance packaging solutions for artificial intelligence (AI) and data center markets in addition to the support of Intel 18A process node. As the demands of AI and data center workloads continue to grow in complexity, ensuring reliable communication between chiplets and 3DICs is becoming increasingly critical. High-speed data transfer and efficient power delivery are essential to meet the performance demands of next-generation semiconductor applications. The semiconductor industry addresses these challenges through emerging open standards, such as Universal Chiplet Interconnect Express ™ (UCIe™) and Bunch of Wires (BoW). These standards define interconnect protocols for chiplets and 3DICs within advanced 2.5D/3D or laminate/organic packages, enabling consistent, high-quality integration across different design platforms. By adopting these standards and verifying chiplets for compliance and link margin, Keysight EDA and Intel Foundry contribute to a growing chiplet interoperability ecosystem. The collaboration aims to reduce development costs, mitigate risk, and accelerate innovation in semiconductor design. Keysight EDA's Chiplet PHY Designer, the latest solution for high-speed digital chiplet design tailored to AI and data center applications, now offers advanced simulation capabilities for the UCIe™ 2.0 standard and introduces support for the Open Computer Project BoW standard. As an advanced, system-level chiplet design and die-to-die (D2D) design solution, Chiplet PHY Designer enables pre-silicon level validation, streamlining the path to tapeout. Suk Lee, VP & GM of Ecosystem Technology Office, Intel Foundry, said: 'Our collaboration with Keysight EDA on EMIB-T silicon bridge technology is a pivotal step in advancing high-performance packaging solutions. By integrating standards like UCIe™ 2.0, we enhance chiplet design flexibility for AI and data center applications, accelerating innovation and ensuring our customers meet next-generation demands with precision.' Niels Faché, Vice President and General Manager, Keysight's Design Engineering Software, said:"Keysight EDA's pioneering Chiplet PHY Designer continues to redefine pre-silicon validation, empowering chiplet designers with rapid, accurate verification. By proactively embracing evolving standards like UCIe 2.0 and BoW, and now with critical support for Intel Foundry's EMIB-T, we're enabling engineers to accelerate innovation and eliminate costly design iterations before manufacturing." See Keysight EDA EMIB-T Solution at Intel Foundry Direct Connect Keysight will demonstrate its EMIB-T workflow for system-level link performance and compliance, featuring Intel Foundry's EMIB-T technology, at Intel Foundry Direct Connect on April 29th in San Jose. At Keysight (NYSE: KEYS), we inspire and empower innovators to bring world-changing technologies to life. As an S&P 500 company, we deliver market-leading design, emulation, and test solutions to help engineers develop and deploy faster, with less risk, throughout the entire product life cycle. We're a global innovation partner enabling customers in communications, industrial automation, aerospace and defense, automotive, semiconductor, and general electronics markets to accelerate innovation to connect and secure the world. Learn more at Keysight Newsroom and
