Latest news with #FinFET-based
GSM Arena
14-05-2025
- GSM Arena
More details about Apple's all-glass iPhone emerge
Apple will celebrate the iPhone's 20th anniversary in 2027 and there has been talk about an updated iPhone 19 Pro model that would offer a major redesign. Bloomberg previously reported that the device would 'make extensive use of glass' and feature a curved design with no display cutouts. A new supply-chain report shared by South Korea's ETNews sheds more light on the mysterious device that's set to offer the biggest design change since the iPhone X from 2017. Xiaomi waterfall display concept from 2021 Apple is reportedly in talks with both Samsung Display and LG Display for its upcoming 'bezel-less' iPhone display panels. The new report describes a 'four-sided bending display' which relocates the bezels to the sides of the device, making the device appear as a single piece of glass when viewed from the front. That sounds a lot like the Xiaomi concept device from 2021. It's also worth mentioning that Xiaomi's concept device had no buttons or ports, which has been a long-standing rumor for Apple. The upcoming iPhone is also said to gain an under-display (UD) camera. According to the new report, the display panel for the iPhone 19 Pro would employ an updated FinFET-based OLED driving chip fabbed on a 16nm process compared to the current 28nm planar process for current iPhone models. Apple is also expected to introduce a solid-state battery with an all-silicon cathode, delivering a drastic boost to battery endurance. As usual with these types of early reports, we'd advise you take the info with a few grains of salt. Source (in Korean)
Yahoo
27-04-2025
- Business
- Yahoo
TSMC discloses N2 defect density — lower than N3 at the same stage of development
When you buy through links on our articles, Future and its syndication partners may earn a commission. TSMC exposed the defect density (D0) of its N2 process technology relative to its predecessors at the same stage of development at its North American Technology Symposium this week. According to the company, the defect density is below that of N3, N5, and N7 manufacturing nodes. In addition, the slide published by ComputerBase reveals that N2 is two quarters away from mass production, which means that TSMC is on-track to start making 2nm-class chips in late Q4 2025, as expected. Although TSMC's N2 is the company's first process technology to adopt gate-all-around (GAA) nanosheet transistors, the node has lower defect density than its predecessors at the same stage of development, two quarters before mass production (MP). The predecessors — N3/N3P, N5/N4, and N7/N6 — all relied on well-known FinFET transistors. So, despite being TSMC's first node using GAA nanosheet transistors, the N2 defect density is getting lower quicker (well, steeper) than that of its predecessors before the high volume manufacturing (HVM) milestone. The chart plots defect density against time, spanning from three quarters before mass production through six quarters after MP. Across all nodes shown — N7/N6 (green), N5/N4 (violet), N3/N3P (red), and N2 (blue) — defect densities drop significantly as production ramps, though at different rates depending on node complexity. Notably, N5/N4 displayed the most aggressive early defect reduction, while N7/N6 showed a more gradual yield improvement. The N2 curve begins with higher initial defect levels than N5/N4 but declines sharply, closely matching the defect reduction trajectory of N3/N3P. The slide emphasizes that production volume and product diversity remain the key drivers for accelerating defect density improvements. Larger production volumes and a wide variety of products using the same process enable faster identification and correction of defect density and yield issues, enabling TSMC to optimize defect learning cycles. TSMC stated that its N2 fabrication technology got more new tape outs than predecessors (as TSMC now risks producing N2 chips for smartphone and HPC customers), so the defect density decrease curve mostly proves that. The fact that N2's defect reduction rate aligns well with previous FinFET-based nodes is particularly significant, given the risk factors associated with introducing an all-new transistor architecture. It suggests that TSMC has successfully transferred its process learning and defect management expertise into the new GAAFET era without major setbacks (at least based on what TSMC discloses). Sign in to access your portfolio
