Latest news with #IntelFoundryDirect2025
Yahoo
03-05-2025
- Business
- Yahoo
Intel hedges its bet for High-NA EUV with the 14A process node — an alternate Low-NA technique has identical yield and design rules
When you buy through links on our articles, Future and its syndication partners may earn a commission. Intel explained the rationale behind its High-NA EUV strategy at its Intel Foundry Direct 2025 conference this week. Despite persistent questions around cost-effectiveness, Intel has championed its use of the new High-NA EUV chipmaking tool with its forthcoming 14A process. However, Intel has not yet fully committed to using the new tool in production, but it has an alternative production flow of its 14A node that uses standard Low-NA EUV as a backup plan. Intel has already received a second high-NA EUV tool, installed in its Oregon fab, and the company says the technology is progressing well. However, due to continuing development, the ~$400 million ASML Twinscan NXE:5000 High-NA EUV machines haven't been used in a production environment yet, so Intel isn't taking any risks. '[..]The first one is, Intel still has the option to have either a Low-NA or a High-NA solution on our 14A technology, and its design-rule compatible, there will be no impact to the customers, depending on the path that we choose. Second, High-NA EUV is performing to the expectations, and we will introduce it at the right time," said Dr. Naga Chandrasekaran, EVP, CTOO & GM of Intel Foundry Technology and Manufacturing. "We already have data on 18A as well as 14A that shows yield parity between our Low-NA-based solution and a High-NA-based solution. So, we are continuing to make progress on the technology front and ensuring that we have the right options available for us to make sure the solution we deliver to our customers has the lowest risk and the best reward in terms of the decisions we make,' Naga explained. Intel will only use High-NA EUV on a small number of layers of the 14A node (the exact number isn't known), while other machines of varying resolutions will be used for the other layers. That means the decision between the two machines will only impact a select portion of the manufacturing process, but Intel says using triple-patterning with a Low-NA EUV (more below) machine instead of High-NA produces the same results. Because both techniques are design-rule compatible, Intel's customers won't have to change their designs regardless of the company's decision on the final manufacturing flow, either with or without High-NA EUV, which helps defray concerns that customers might have with Intel embracing an as-yet unproven production technology. Additionally, Intel's claim that both production flows offer the same yields signals that there won't be severe time-to-market repercussions if High-NA EUV development hits a snag, or if Intel chooses not to deploy it due to economics. Employing multipatterning often reduces yields, but Intel's claim of yield parity speaks to the advances of modern multipatterning, particularly in the field of overlay technology. Most of the public-facing conversations about High-NA EUV have centered around cost, there's plenty of industry speculation that High-NA isn't as cost-effective as multi-patterning with Low-NA EUV, but there are still numerous technological hurdles to bringing the machines into production. Most of the challenges center around the universe of complementary technologies required to make High-NA viable, like resists, photomasks, and computational lithography, among others, which have to be optimized for the new machines. However, Intel adopted ASML's machine first to get a leg up on the competition, and it has already produced 30,000 wafers using High-NA lithography during the development phase. As a representative explained later in the event, Intel still sees significant cost savings due to eliminating around 40 process steps. 'Finally, I want to talk about High-NA EUV. Why do we do this? It's very simple; It's lower cost. In the middle picture, you see a pattern that has been generated by a single pass High-NA EUV and a pitch that is comparable to the pitch that we need for 14A. The right-hand side shows a very similar pattern generated with a traditional approach, where we use three EUV exposures [triple patterning], and overall about 40 process steps to generate this pattern." "So, overall, we see much shorter, simpler flow, and this is the type of application where we use High-NA in 14A, which reduces the cost compared to the multi-pass 0.33 NA EUV [Low-NA]. Additionally, this provides the option to de-populate the metal layers and get additional performance enhancement.' Intel didn't specify whether or not its comparisons are based on a full-reticle-sized print. High-NA can only print half of a reticle at a time, requiring two prints to create one reticle-sized processor and relying upon stitching to bring the two prints together into a single cohesive unit. In contrast, die that are equal to or smaller than a half-reticle size will only require one print with High-NA EUV. In contrast, Low-NA EUV machines can process a full reticle-sized die in a single print. Intel has plenty of scar tissue from its 10nm node failures that ultimately ended in the company losing its chipmaking lead over TSMC, and it chalks the 10nm issues up to making too many big bets on new manufacturing techniques and technologies at once. The decision to develop an alternative Low-NA production flow is designed to prevent repeating those past mistakes, and Intel has also de-risked other types of advances by developing alternative solutions in the past. For instance, the company developed its new backside power delivery system with the 18A node, an industry first, while simultaneously developing gate-all-around (GAA) transistors, a first for Intel. To ensure a backup plan, the company employed a more robust de-risking strategy with its 18A process that included developing an internal-only trial process node without backside power. However, development went well with both GAA and backside power delivery, so Intel pushed forward with the full version of the 18A node. Intel rival TSMC has confirmed it will not use High-NA with its competing A14 node, and it hasn't indicated when it will employ the new High-NA EUV tool in volume production. Intel had originally planned to use High-NA with its 18A process, which arrives before the 14A node. Intel later changed those plans, saying that the process node's unexpectedly fast development meant the machines wouldn't be ready in time.
Yahoo
30-04-2025
- Business
- Yahoo
Intel Foundry Roadmap Update - New 18A-PT variant that enables 3D die stacking, 14A process node enablement
When you buy through links on our articles, Future and its syndication partners may earn a commission. Intel's new CEO Lip Bu-Tan took to the stage at the company's Intel Foundry Direct 2025 event here in San Jose, California, to outline the company's progress on its foundry initiative. Tan announced that the company is now engaging lead customers for its upcoming 14A process node (1.4nm equivalent), the follow-on generation of its 18A process node. Intel already has several customers with plans to tape out 14A test chips, which now come with an enhanced version of the company's backside power delivery technology dubbed PowerDirect. Tan also revealed that the company's crucial 18A node is now in risk production with volume manufacturing on schedule for later this year. Intel also revealed that its new 18A-P extension, a high-performance variant of the 18A node, is now running through the fab with early wafers. Additionally, the company is developing a new 18A-PT variant that supports Foveros Direct 3D with hybrid bonding interconnects, enabling the company to stack dies vertically on top of its most advanced leading-edge node. The Foveros Direct 3D technology is a key development because it provides a capability that rival TSMC already uses in production, most famously in AMD's 3D V-Cache products. In fact, Intel's implementation matches TSMC's offering in critical interconnect density measurements. On the mature-node side of the operation, Intel Foundry has its first production 16nm tapeout in the fab now, and the company is also now engaging customers for the 12nm node it is developing in partnership with UMC. Perhaps the most important developments at the show revolve around Intel's continued expansion with EDA and intellectual property (IP) partners that provide the critical tools and IP blocks that enable its customers to develop new designs with industry-standard design flows and tools. The company has also expanded its Intel Foundry Accelerator Alliance program to include the Chiplet Alliance and Value Chain Alliance programs. Intel Foundry's progress comes during turbulent times in the semiconductor industry as geopolitical divisions threaten to fracture the global chip supply chain. Intel is currently the only US-based domestic supplier of leading-edge process node technology and advanced packaging capacity, a key advantage as tensions between China and TSMC continue to escalate. Despite TSMC's expansion of production in the US, a recent law passed by Taiwan now prevents the company from producing its most cutting-edge tech in the United States, leaving Intel as the only domestic foundry with both leading-edge chip production and R&D. Naga Chandrasekaran, the Chief Technology and Operations Officer of Intel Foundry, and Kevin O'Buckley, the General Manager of Foundry Services, are also slated to deliver keynotes during the event, providing more details about the technology and roadmaps. We will update this article with additional information as it becomes available, but we have plenty to share to get started. Let's take a closer look at Intel's progress. Intel's 14A, the next generation after 18A, is already in the works and scheduled for risk production in 2027. If all goes to plan, 14A will be the industry's first node to employ High-NA EUV lithography. TSMC's competing A14 (1.4nm-class) node is expected to arrive in 2028, but the Taiwanese company will not utilize High-NA for production. Intel has already shared early versions of the Process Design Kit (PDK), a set of data, documentation, and design rules that enables the design and validation of a processor design, with its lead 14A customers. Intel states that multiple customers have already indicated their intention to build chips using the 14A process node. Intel's 14A will have a second-generation version of its PowerVia backside power delivery technology. The new PowerDirect implementation is a more advanced and complex scheme that delivers power directly to each transistor's source and drain through specialized contacts, which minimizes resistance and maximizes power efficiency. This is a more direct and efficient connection than Intel's current PowerVia scheme, which connects to the contact level of the transistors with Nano TSVs. TSMC's N2 node does not include backside power delivery; however, with A16, the company will employ a direct-contact backside power delivery network, dubbed Super Power Rail (SPR). A16 is essentially a derivative of the N2P node with SPR. The A16 node is expected to enter production in late 2026. TSMC's A14 will not leverage a backside power design methodology. Intel's 18A node is the mainstream variant, but the company also has several 'line extensions' of the node, designated by different suffixes. These flavors of the underlying node are tailored for different use cases. Intel has a new 18A variant up its sleeve; the new 18A-PT node that will provide the same performance and efficiency benefits as the performance-oriented 18A-P, but adds in Foveros Direct 3D hybrid bonding. This bump-less copper-to-copper bonding technique (meaning it doesn't use microbumps or solder to connect the two dies) fuses chips together with through-silicon vias (TSVs). Intel's implementation will employ a pitch of less than 5 microns, a distinct improvement over its initial goal of a 10um pitch by 2023, to fuse chiplets on top of the 18A-PT die. The pitch is a measurement of the center-to-center spacing between the interconnects, and lower values indicate higher density, which is better. Notably, AMD uses TSMC's SoIC-X technology, a similar hybrid bonding approach, to fuse an L3 chiplet atop its X3D processors with a 9 micron bump pitch. TSMC's SOIC-X tech currently ranges from 4.5 to 9 microns, but the company has a 3-micron pitch offering on the roadmap for 2027. If productized effectively and on schedule, Intel's Foveros Direct 3D will dramatically improve its positioning against TSMC's packaging technology. Intel's Clearwater Forest will be its first to use Foveros Direct 3D packaging, but the company hasn't disclosed the pitch for that specific product yet. Notably, TSVs are typically only included in the base die, and Clearwater Forest uses Intel 3-T for the base die with the Intel 18A compute dies stacked on top. Enabling TSVs for 18A will thus allow it to also have dies stacked atop, and SRAM cache is a logical use case. Image 1 of 2 Image 2 of 2 As we reported last month, Intel's 18A (1.8 nm-equivalent) process node has entered risk production, marking the commencement of the first low-volume production runs of the node, with High Volume Manufacturing (HVM) scheduled for the end of the year. Intel did not specify which processors had begun production, but the timing generally aligns with expectations for its Panther Lake processors, which are expected to arrive at the end of the year. Intel's first 18A production will come from its Oregon fabs, but the company has already 'run the [18A] lot' through its Arizona fab, indicating it will soon begin production there as well. The 18A node is the first in the industry to be productized with both a PowerVia backside power delivery network (BSPDN) and RibbonFET gate-all-around (GAA) transistors. PowerVia provides optimized power routing on the back of the chip to improve performance and transistor density. RibbonFET also offers better transistor density, along with faster transistor switching, in a smaller area through the use of four vertical nanosheets surrounded entirely by the gate. The 18A node enters HVM in roughly the same timeframe as TSMC's competing 2nm N2 node. However, TSMC's N2 node does not come with a backside power delivery network, but it does have GAA technology with three vertical nanosheets. There have been some basic comparisons between the process nodes made based on presentations at a recent industry event. The general takeaway is that Intel's node is faster and lower-power than TSMC's, though TSMC retains the edge in density (and presumably cost). However, these distinctions could vary depending on the specific implementation in different chip designs. Intel divulged today that it has wafers of its high-performance 18A-P node in the fab. This 18A variant features an optimized power and frequency curve, providing an 8% improvement in performance per watt. This can be leveraged as either higher clock speeds or lower power consumption at the same performance, depending upon chip-specific tuning. The 18A-P node is design rule-compatible with the 18A node, easing the design process for customers. Intel is already collaborating with Electronic Design Automation (EDA) software vendors to enable broad support for industry-standard design tools, and it is also working with Intellectual Property (IP) designers to provide the necessary IP blocks, thereby simplifying implementation. Intel Foundry not only addresses the leading edge of technology, but it is also working on several mature nodes. Intel's 16nm node, which is essentially a version of its 22FFL node that leverages industry standard design tools and PDKs, has a tapeout in the fab now. Intel is also continuing its work with partner UMC to develop a 12nm node that will be produced in three of Intel's Arizona fabs beginning in 2027. In fact, Intel is currently engaging lead customer for this node. 12nm will be used primarily for mobile communication infrastructure and networking applications. Intel canceled high volume manufacturing of the 20A node as a cost-cutting measure, but the company is now on the cusp of of production with with its18A node, marking a critical milestone as it looks to regain the manufacturing lead over TSMC. The addition of new line extensions, with the die-stacking-capable 18A-PT being a particularly strong advance, will help the company to further broaden its appeal to potential foundry customers. The development of the company's 14A node is also well underway, signifying that the company is on track to providing a steady cadence of new nodes and features to the roadmap. We haven't yet heard any new details about Intel's plans for its 10A (1nm-class) process node yet, which is expected to begin development in 2027. Intel's press release also doesn't mention any new progress on its Intel 3 node, but we expect more details to emerge throughout the day. Intel's event is focused heavily on displaying its broad portfolio of EDA, IP, and services driven by an ecosystem of indsutry stalwarts, like Synopsys and Cadence. The new Intel Foundry Chiplet Alliance is also an important development that will enable customers to mix-and-match chiplets into their design based upon interoperable and validated designs. Intel's advanced packaging services are also of particular importance as they provide the fastest on-ramp to meaningful revenue generation. Intel did mention that it will make its 3D stacking Foveros implementation available to foundry customers, and noted a new partnership with Amkor. However, details are slight for now. We'll update this article as more information becomes available.
