Latest news with #NorthAmericanTechnologySymposium
Globe and Mail
30-04-2025
- Business
- Globe and Mail
Taiwan Semi Just Announced Its New A14 Tech. Should You Buy TSM Stock Now?
Taiwan Semiconductor Manufacturing (TSM) is the largest integrated circuit foundry in the world. It takes proprietary circuit designs from other companies and then produces them using advanced processes. Given this dominance in the foundry market, Taiwan Semi is often considered one of the most globally important semiconductor companies. TSM stock has had an underwhelming year so far, down roughly 17% in the year to date and nearly 30% off its 52-week high. Taiwan Semi shares appear to be recovering, up about 8% over the last five sessions. TSMC Reveals New A14 Process TSMC unveiled its latest logic process technology, A14, at its North American Technology Symposium in Santa Clara, California. This technology will improve smartphones' onboard artificial intelligence (AI) capabilities and enhance the development of AI applications. The A14 technology will not be utilized in production until 2028. The N2 process will be entering production later this year and compared to the N2 process, A14 is 15% faster in terms of speed, has 20% greater logic density, and is 30% more power efficient. A14's name refers to 14 angstrom, or 1.4 nanometers, while the N2 is 2 nanometers. At present, market heavyweights such as Apple (AAPL), Advanced Micro Devices (AMD), Nvidia (NVDA), and Intel (INTC) are all expected to use the N2 process for their chips. 'TSMC's cutting-edge logic technologies like A14 are part of a comprehensive suite of solutions that connect the physical and digital worlds to unleash our customers' innovation for advancing the AI future,' said TSMC CEO C.C. Wei. During the Symposium, TSMC also introduced new logic, specialty, and 3D chip stacking techniques that can be used in high-performance computing, smartphones, self-driven automotive, and AI functionality in electronics and other appliances. TSMC's Q1 Results TSMC reported its first-quarter results on April 17, posting EPS of $2.12 for Q1 2025, surpassing analyst expectations. The company achieved revenue of $25.53 billion, marking a 41.6% year-over-year increase. However, revenue fell short of the previous quarter, showing a 3.4% decline. The gross margin for the quarter stood at 58.8%, while the operating margin reached 48.5%, and the net profit margin was 43.1%. Advanced technologies like 3-nanometer and 5-nanometer processes contributed significantly to wafer revenue, accounting for 73% of total revenue. Looking ahead, TSMC expects Q2 2025 revenue to range between $28.4 billion and $29.2 billion, supported by strong demand for its cutting-edge 3-nm and 5-nm technologies. Gross profit margin is projected to be between 57% and 59%, while operating profit margin is anticipated to range from 47% to 49%. The company remains cautious about potential risks from tariff policies but is optimistic about sustained growth in AI-related demand. Analyst Ratings on TSM Stock Analysts are very fond of the blockbuster semiconductor stock. TSM has a consensus 'Strong Buy' from analysts with a mean price target of $229.38, reflecting upside potential of 40% from the current price level. The stock is under the watch of 11 analysts and has received eight 'Strong Buy' ratings, two 'Moderate Buy' ratings, and one 'Hold' rating.
Yahoo
27-04-2025
- Business
- Yahoo
TSMC discloses N2 defect density — lower than N3 at the same stage of development
When you buy through links on our articles, Future and its syndication partners may earn a commission. TSMC exposed the defect density (D0) of its N2 process technology relative to its predecessors at the same stage of development at its North American Technology Symposium this week. According to the company, the defect density is below that of N3, N5, and N7 manufacturing nodes. In addition, the slide published by ComputerBase reveals that N2 is two quarters away from mass production, which means that TSMC is on-track to start making 2nm-class chips in late Q4 2025, as expected. Although TSMC's N2 is the company's first process technology to adopt gate-all-around (GAA) nanosheet transistors, the node has lower defect density than its predecessors at the same stage of development, two quarters before mass production (MP). The predecessors — N3/N3P, N5/N4, and N7/N6 — all relied on well-known FinFET transistors. So, despite being TSMC's first node using GAA nanosheet transistors, the N2 defect density is getting lower quicker (well, steeper) than that of its predecessors before the high volume manufacturing (HVM) milestone. The chart plots defect density against time, spanning from three quarters before mass production through six quarters after MP. Across all nodes shown — N7/N6 (green), N5/N4 (violet), N3/N3P (red), and N2 (blue) — defect densities drop significantly as production ramps, though at different rates depending on node complexity. Notably, N5/N4 displayed the most aggressive early defect reduction, while N7/N6 showed a more gradual yield improvement. The N2 curve begins with higher initial defect levels than N5/N4 but declines sharply, closely matching the defect reduction trajectory of N3/N3P. The slide emphasizes that production volume and product diversity remain the key drivers for accelerating defect density improvements. Larger production volumes and a wide variety of products using the same process enable faster identification and correction of defect density and yield issues, enabling TSMC to optimize defect learning cycles. TSMC stated that its N2 fabrication technology got more new tape outs than predecessors (as TSMC now risks producing N2 chips for smartphone and HPC customers), so the defect density decrease curve mostly proves that. The fact that N2's defect reduction rate aligns well with previous FinFET-based nodes is particularly significant, given the risk factors associated with introducing an all-new transistor architecture. It suggests that TSMC has successfully transferred its process learning and defect management expertise into the new GAAFET era without major setbacks (at least based on what TSMC discloses). Sign in to access your portfolio
Yahoo
25-04-2025
- Business
- Yahoo
TSMC mulls massive 1000W-class multi-chiplet processors with 40X the performance of standard models
When you buy through links on our articles, Future and its syndication partners may earn a commission. You might often think of processors as being relatively small, but TSMC is developing a version of its CoWoS technology that will enable its partners to build multi-chiplet assemblies that will be 9.5-reticle sized (7,885 mm^2) and will rely on 120×150 mm substrates (18,000 mm^2), which is slightly larger than the size of a CD case. TSMC claims these behemoths could offer up to 40 times the performance of a standard processor. Virtually all modern high-performance data center-grade processors use multi-chiplet designs, and as demands for performance increase, developers want to integrate even more silicon into their products. In an effort to meet demand, TSMC is enhancing its packaging capabilities to support significantly larger chip assemblies for high-performance computing and AI applications. At its North American Technology Symposium, TSMC unveiled its new 3DFabric roadmap, which aims to scale interposer sizes well beyond current limits. Currently, TSMC CoWoS offers chip packaging solutions that enable interposer sizes of up to 2831 mm^2, which is approximately 3.3 times larger than the company's reticle (photomask) size limit (858 mm^2 per EUV standard, with TSMC using 830 mm^2). This capacity is already utilized by products like AMD's Instinct MI300X accelerators and Nvidia's B200 GPUs, which combine two large logic chiplets for compute with eight stacks of HBM3 or HBM3E memory. But that's not enough for future applications. Sometimes next year, or a bit later, TSMC plans to introduce the next generation of its CoWoS-L packaging technology, which will support interposers measuring up to 4,719 mm^2, roughly 5.5 times larger than the standard reticle area. The package will accommodate up to 12 stacks of high-bandwidth memory and will require a larger substrate measuring 100×100 mm (10,000 mm^2). The company expects that solutions built on this generation of packaging will deliver more than three and a half times the compute performance of current designs. While this solution may be enough for Nvidia's Rubin GPUs with 12 HBM4 stacks, processors that will offer more compute horsepower will require even more silicon. Looking further ahead, TSMC intends to scale this packaging approach even more aggressively. The company plans to offer interposers with an area of up to 7,885 mm^2, approximately 9.5 times the photomask limit, mounted on a 120×150 mm substrate (for context, a standard CD jewel case measures approximately 142×125 mm). This represents an increase from an 8x-reticle-sized multi-chiplet assembly on a 120×120mm substrate that TSMC presented last year, and this increase likely reflects the requests from the foundry's customers. Such a package is expected to support four 3D stacked systems-on-integrated chips (SoICs, e.g., an N2/A16 die stacked on top of an N3 logic die), twelve HBM4 memory stacks, and additional input/output dies (I/O Die). However, TSMC has customers who demand extreme performance and are willing to pay for it. For them, TSMC offers its System-on-Wafer (SoW-X) technology, which enables wafer-level integration. For now, only Cerebras and Tesla use wafer-level integration for their WFE and Dojo processors for AI, but TSMC believes there will be customers beyond these two companies with similar requirements. Without a doubt, 9.5-reticle-sized or wafer-sized processors are hard to build and assemble. But these multi-chiplet solutions require high-current kilowatt-level power delivery, and this is getting harder for server makers and chip developers, so it needs to be addressed at the system level. At its 2025 Technology Symposium, TSMC outlined a power delivery strategy designed to enable efficient and scalable power delivery at kilowatt-class levels. To address processors with kilowatt-class power requirements, TSMC wants to integrate monolithic power management ICs (PMICs) with TSVs made on TSMC's N16 FinFET technology and on-wafer inductors directly into CoWoS-L packages with RDL interposers, enabling power routing through the substrate itself. This reduces distance between power sources and active dies, lowering parasitic resistance and improving system-wide power integrity. TSMC claims that its N16-based PMIC can easily handle fine-grained voltage control for dynamic voltage scaling (DVS) at the required current levels, achieving up to five times higher power delivery density compared to conventional approaches. In addition, embedded deep trench capacitors (eDTC/DTC), built directly into the interposer or silicon substrate, provide high-density decoupling (up to 2,500 nF/mm^2) to improve power stability by filtering voltage fluctuations close to the die and ensure reliable operation even under rapid workload changes. This embedded approach enables effective DVS and improved transient response, both of which are critical for managing power efficiency in complex, multi-core, or multi-die designs. In general, TSMC's power delivery approach reflects a shift toward system-level co-optimization, where power delivery to silicon is treated as an integral part of the silicon, packaging, and system design, not a separate feature of each component. The move to much larger interposer sizes will have consequences for system design, particularly in terms of packaging form factors. The planned 100×100 mm substrate is close to the physical limits of the OAM 2.0 form factor, which measures 102×165 mm. The subsequent 120×150 mm substrate will exceed these dimensions, likely requiring new standards for module packaging and board layout to accommodate the increased size. Beyond physical constraints and power consumption, these huge multi-chiplet SiPs generate an enormous amount of heat. To address this, hardware manufacturers are already exploring advanced cooling methods, including direct liquid cooling (a technology already adopted by Nvidia for its GB200/GB300 NVL72 designs) and immersion cooling technologies, to handle the thermal loads associated with multi-kilowatt processors. However, TSMC can't address that problem on the chip or SiP level — at least for now.
Yahoo
24-04-2025
- Automotive
- Yahoo
TSMC's New A14 Chip Targets Future AI in Phones and Smart Devices
Taiwan Semiconductor Manufacturing (NYSE:TSM) introduced its next-generation chip technologydubbed A14at its North American Technology Symposium in Santa Clara, California on Wednesday. The new process aims to improve on-device artificial intelligence capabilities and enhance overall computing power in future smartphones and AI applications. Warning! GuruFocus has detected 4 Warning Signs with GS. The A14, which won't enter production until 2028, builds on TSMC's upcoming N2 process (scheduled for later this year). According to the company, A14 chips will deliver 15% faster performance, 20% higher logic density, and consume up to 30% less power compared to the N2. The A14 refers to a 14-angstrom nodeequivalent to 1.4 nanometersversus the 2-nanometer scale of N2. Major tech firms including Apple (NASDAQ:AAPL) Advanced Micro Devices (NASDAQ:AMD), Intel (NASDAQ:INTC), and Nvidia (NASDAQ:NVDA) are all expected to use the N2 process in their future chip designs. TSMC CEO C.C. Wei highlighted the company's roadmap in pushing forward chip innovation for AI and high-performance computing. In addition to the A14, TSMC also showcased updates in packaging, specialty chips, and 3D stacking, all aimed at powering AI in devices ranging from smartphones to self-driving cars. This article first appeared on GuruFocus. Sign in to access your portfolio
