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Upgrades coming for Subis senior activity centre, says S'wak deputy minister
Upgrades coming for Subis senior activity centre, says S'wak deputy minister

Borneo Post

time16-05-2025

  • General
  • Borneo Post

Upgrades coming for Subis senior activity centre, says S'wak deputy minister

Rosey (seated, centre) and recipients pose for a group photo after MRP cheque handover. MIRI (May 17): Senior citizens in Subis will soon enjoy improved facilities for their activities following approved plans to upgrade the existing senior citizen activity centre (Pawe), said Deputy Minister of Women, Childhood and Community Wellbeing Development, Datuk Rosey Yunus. The first approved project, she revealed, involves constructing a covered shed to connect the Pawe Building and the Community-based Rehabilitation Centre (PDK). 'There is an empty area between the two buildings. So, the plan is to build an open hall at a cost of RM200,000. It would be a good place for both Pawe and PDK to hold activities,' said Rosey after handing over Minor Rural Project (MRP) grants to eight recipients at Pawe building on Wednesday. Another approved plan, she added, is to upgrade the existing Pawe building, including floor repairs and improvements to the safety fencing. She emphasised the importance of these upgrades, noting that the Pawe is located in a remote area, far from the town centre. Therefore, the safety and comfort of senior citizens are given top priority to ensure they can carry out their activities in a conducive environment. 'These infrastructure improvements are in line with the government's inclusive approach to encourage active participation among senior citizens in the community, and to ensure they age healthily and with dignity. 'We want our senior citizens to stay active and healthy ― not just sit at home. That is why I would like to urge those aged 60 and above to register as Pawe members and make full use of the facilities provided,' she said. The Bekenu assemblywoman added that the construction project will be implemented by the Public Works Department (JKR), and is expected to be completed within the year after the appointment of contractors is finalised. The total amount of grants disbursed at the simple handover ceremony was RM75,838.00. The recipients were Special Development Committee for Zone Saeh (RM8,000); JKKK Kampung Bulau (RM5,000); Batu Niah Che Yan Khor Moral Uplifting Society (RM3,838); SK Beliau Isa Parents Teachers Association (RM10,000); SK Bekenu Parents Teachers Association (RM10,000); BBP Lutong's Musolla Al-Azhar (RM15,000); Pawe Subis (RM4,000); and Jawatankuasa Perhubungan Komuniti Subis (RM20,000). Pawe Rosey Yunus Senior Citizen Activity Centre Subis upgrades

QuickLogic Corp (QUIK) Q1 2025 Earnings Call Highlights: Strategic Partnerships and Revenue ...
QuickLogic Corp (QUIK) Q1 2025 Earnings Call Highlights: Strategic Partnerships and Revenue ...

Yahoo

time14-05-2025

  • Business
  • Yahoo

QuickLogic Corp (QUIK) Q1 2025 Earnings Call Highlights: Strategic Partnerships and Revenue ...

Release Date: May 13, 2025 For the complete transcript of the earnings call, please refer to the full earnings call transcript. QuickLogic Corp (NASDAQ:QUIK) secured the first of two EFPGA hard IP contracts for Intel 18A designs, with the second expected in Q4. The company has been recognized as the first available source for EFPGA hard IP for Intel 18A, enhancing its market position. QuickLogic Corp (NASDAQ:QUIK) has been named a partner in the Intel Foundry Accelerator Chilet Alliance, indicating strong industry partnerships. The inclusion of EFPGA hard IP in Faraday's new SOC development platform is expected to generate revenue in the second half of 2025. QuickLogic Corp (NASDAQ:QUIK) anticipates solid revenue growth, non-gap profitability, and positive cash flow for the full year 2025. Revenue guidance for Q2 2025 is lower than anticipated due to a delay in a large IP contract, impacting short-term financial performance. Total revenue for Q1 2025 was down 28% from Q1 2024, indicating a decline in year-over-year performance. Non-gap gross margin in Q1 was significantly lower than previous quarters, affected by cost allocations. The company reported a non-gap net loss of $1.1 million for Q1 2025, compared to a net income in the previous year. QuickLogic Corp (NASDAQ:QUIK) continues to face risks related to market acceptance of new products and intense competition. Warning! GuruFocus has detected 5 Warning Signs with QUIK. Q: Can you discuss the progress and revenue expectations related to Intel 18A and its applications in commercial and defense markets? A: Brian Faith, CEO: We have been working on Intel 18A since we got access to the PDK version 1.0. Our efforts have led to a robust IP core, particularly appealing to the defense industrial base. We anticipate revenue from Intel 18A licenses this fiscal year, with royalties expected next year. The process is considered de-risked, and we are the only provider of EFPGA hard IP for Intel 18A, which is attracting significant interest from both commercial and defense sectors. Q: What are the key drivers for QuickLogic's anticipated revenue growth and profitability in the second half of 2025? A: Brian Faith, CEO: The growth will be driven by new IP contracts, including those related to Intel 18A and strategic radar contracts. These contracts have higher average selling prices compared to previous years. Our automated Australis platform allows us to adapt designs efficiently, supporting this growth with our current team size. Q: Can you elaborate on the storefront opportunities and their potential impact on QuickLogic's business? A: Brian Faith, CEO: We have several storefront opportunities, including the strategic radar contract and a direct-to-storefront contract. We are also exploring new opportunities from the Intel Direct Connect conference. Our EFPGA technology is well-suited for these applications, and we expect these storefront opportunities to contribute significantly to our revenue. Q: How does QuickLogic's technology help reduce costs in the defense market, particularly regarding verification and integration? A: Brian Faith, CEO: Our technology allows for the integration of discrete FPGA functions into a single chip, reducing size, weight, and power (SWaP) requirements. This integration also lowers verification costs by consolidating testing to a single chip, which is crucial for defense applications where multiple chips would otherwise require extensive testing. Q: What is the nature of QuickLogic's partnership with Faraday, and what markets are you targeting together? A: Brian Faith, CEO: Faraday will be the primary interface with customers, focusing on low-power industrial and IoT applications. We support them with use cases and training. The partnership aims to leverage our EFPGA technology in Faraday's SOC development platform, targeting applications that require low power and edge computing capabilities. For the complete transcript of the earnings call, please refer to the full earnings call transcript. This article first appeared on GuruFocus. Error in retrieving data Sign in to access your portfolio Error in retrieving data Error in retrieving data Error in retrieving data Error in retrieving data

Mounting calls for stronger law to protect disabled children
Mounting calls for stronger law to protect disabled children

The Sun

time09-05-2025

  • The Sun

Mounting calls for stronger law to protect disabled children

PUTRAJAYA: PUTRAJAYA: Calls are mounting for the government to introduce a dedicated Child Act for children with disabilities, to ensure stronger protections, reinforced rights and swifter justice, particularly following institutional abuse cases. Senator Isaiah D. Jacob criticised systemic failings in the protection of individuals with disabilities, stating that the government had failed to prioritise their welfare in abuse cases involving these children. His visit yesterday to the Attorney-General's Chambers to submit a memorandum to Attorney-General Datuk Mohd Dusuki Mokhtar underscored grave concerns over what he described as a miscarriage of justice and a breakdown in the child protection system. He called for a thorough reinvestigation of an abuse case. 'The abuse is not alleged, it is proven. The perpetrator has admitted guilt in open court. Yet instead of being charged under the Child Act 2001, she was charged under a general provision of the Penal Code. 'This raises a deeply troubling question: Are children with disabilities being denied equal protection under our laws? If so, this is not merely a legal oversight, it is institutional discrimination,' he said. The memorandum detailed a confirmed case of physical abuse involving Adam and Anaqi, both with Down syndrome, who were students at a Community-Based Rehabilitation Centre (PDK) in the area. Medical reports confirmed that Adam sustained injuries consistent with physical abuse. Anaqi was subjected to repeated harm at the same centre, including bruises, head trauma and facial swelling. A teacher from the centre later pleaded guilty in the Magistrate's Court and was convicted under Section 323 of the Penal Code. She was fined RM2,000, with an alternative option of two months' imprisonment. She opted to pay. Isaiah argued that the failure to apply the Child Act 2001 was a serious concern, noting that Section 31(1)(a) allows for up to 10 years' imprisonment, a fine of up to RM20,000 or both, for abuse or neglect. 'We need a special Act to protect children with disabilities. In this case, a child was abused in a rehabilitation centre, yet justice has not been served.' He also urged the ministry to immediately shut down unlicensed and unregistered centres that endanger vulnerable children, stressing that action must not wait until another tragedy occurs. Isaiah revealed that while there are 573 registered PDKs across Malaysia, many others could be operating without proper oversight. 'So far, I've personally investigated and identified one such centre. I'll keep visiting every PDK I can. As a PWD (persons with disabilities) myself, I feel a responsibility to ensure the safety and well-being of those with disabilities. 'I've written to the ministry and that centre is still operating. That is unacceptable. Why hasn't the ministry shut it down?' He added that many abuse cases go unreported because parents fear retaliation against their children if they speak out. Isaiah also called for separate legal provisions for rehabilitation centres, arguing that their nature differs significantly from regular childcare facilities. 'Children in these facilities are not like other children, so the laws and penalties must reflect that. 'The punishment applied to normal children should not be used for children with disabilities. That is my main point, we need a specific Act to protect children with disabilities.' He urged the Attorney-General's Chambers to review the case thoroughly and ensure that the rights of children with disabilities are fully upheld under the law.

Autism in Malaysia: Nearly 60,000 children diagnosed, registered as of 2024
Autism in Malaysia: Nearly 60,000 children diagnosed, registered as of 2024

New Straits Times

time01-05-2025

  • Health
  • New Straits Times

Autism in Malaysia: Nearly 60,000 children diagnosed, registered as of 2024

KUALA LUMPUR: A total of 58,708 children diagnosed with autism have been registered with the Welfare Department as of December 31 last year. Over one-fifth (12,905) of the children diagnosed with autism are in Selangor, followed by Johor (6,879), Kuala Lumpur (6,876), Sabah (5,210), Sarawak (4,563), and Kedah (3,687). In Perak, there are 3,642 children, followed by Penang (2,914), Pahang (2,785), Kelantan (2,520), Melaka (2,025), Negeri Sembilan (1,974), Terengganu (1,797), Perlis (488) and Labuan (443). These children are among the 751,421 individuals registered with the Welfare Department as persons with disabilities. Women, Family and Community Development Minister Datuk Seri Nancy Shukri said there is an upward trend in the number of children diagnosed with autism compared to other categories. "Without support, these children will face challenges in being independent, integrating into society, and gaining access to education or employment," she said. She added that early intervention is critical for children with autism. "This situation could also lead to increased dependency on government aid and social welfare, which would ultimately impact the country's overall development," she said. Nancy said various initiatives, including the Early Intervention Programme and the Community-Based Rehabilitation Programme (PDK), have been introduced to provide training and early education to children with special needs. She added that her ministry is also working with the Education Ministry to ensure children with special needs receive inclusive education suited to their needs. Nancy said the ministry, through the Welfare Department, runs seven institutions catering to different categories of disabilities and works closely with NGOs such as the National Autism Society of Malaysia to run PDKs and Independent Living Centres (ILCs). As of 2024, a total of 19,909 people with disabilities have received training at 573 PDKs and six ILCs nationwide.

Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications

Yahoo

time30-04-2025

  • Business
  • Yahoo

Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications

Highlights: Significantly expanded portfolio of Cadence design IP optimized for Intel's advanced technologies AI-driven digital and analog/custom EDA solutions certified for Intel 18A technology PDK, delivering optimized PPA Co-developed advanced packaging reference design flow for Intel Foundry's EMIB and EMIB-T technology certified for latest PDK Engagement underway on early design technology co-optimization for Intel 14A-E Joins the Intel Foundry Chiplet Alliance as a founding member SAN JOSE, Calif., April 29, 2025--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence® digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK). These advancements are being showcased today at Intel Foundry Direct Connect, underscoring Cadence's continued leadership in driving industry innovation for artificial intelligence and machine learning (AI/ML), high-performance computing (HPC) and advanced mobility applications through its strategic partnership with Intel Foundry. Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. With this collaboration, joint customers can achieve exceptional power, performance and area (PPA) efficiencies, accelerating time to market for cutting-edge system-on-chip (SoC) designs. The latest additions to Cadence's broad portfolio of design IP in Intel 18A/18A-P technologies are available shortly and include: 224G SerDes with long-range performance for Universal Accelerator Link™ (UALink™) and Ultra Ethernet™, the latest standards for scaling up and out accelerator networks in AI factories DDR5 – 12.8G with MRDIMM Gen2 support, supporting the latest in DRAM technology for AI applications Universal Chiplet Interconnect Express™ (UCIe™) 1.1 48G, which seamlessly facilitates multi-die system-in-package (SiP) integration for scalable chiplet architectures at high data rates Advanced computing and peripheral connectivity IP compatible with the latest consumer standards, enabling scalable embedded applications for a wide range of consumer and mobility requirements: 10G multi-protocol SerDes PHY, supporting PCI Express® (PCIe®) 3.0, DisplayPort and Ethernet eUSB2 v2.0 MIPI® SoundWire® I3S Cadence's expanded portfolio also includes a range of design IP already available in the Intel 18A technology family: 112G Extended Long-Reach SerDes with superior bit error rate (BER) performance for robust data integrity over longer distances; 64G MP PHY for PCIe 6.0, CXL 3.0 and 56G Ethernet; LPDDR5X/5 – 8533 Mbps with multi-standard support; and UCIe 1.0 16G for advanced packaging. Mutual customers now have a broad range of IP options for their AI/ML, HPC and mobility applications leveraging Intel 18A/18A-P RibbonFET and PowerVia implementation. In addition to the new IP for Intel 18A and 18A-P technologies, Cadence's comprehensive suite of AI-driven design and analog/custom design solutions has been certified for the latest Intel 18A node PDK. This includes the complete AI-driven Cadence RTL-to-GDS flow, featuring a range of robust solutions such as the Cadence Cerebrus® Intelligent Chip Explorer, Genus™ Synthesis Solution, Innovus™ Implementation System, Quantus™ Extraction Solution, Quantus Field Solver, Tempus™ Timing Solution and Pegasus™ Verification System. The flow also includes custom IC design solutions such as Cadence Virtuoso® Studio, the integrated Spectre® Platform and the Voltus™-XFi Custom Power Integrity Solution. Meanwhile, Cadence and Intel Foundry are engaging in early design technology co-optimization for Intel 14A-E to establish the readiness of Cadence EDA flows for the next-generation advanced node. In addition, Cadence and Intel Foundry have also partnered to develop an advanced packaging workflow leveraging Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology. This solution streamlines the integration of complex multi-chiplet architectures—eliminating data conversion, shortening design cycles and enabling concurrent activities with early thermal, signal integrity and power modeling. It also ensures compliance with standards, reduces risks and simplifies adoption of Intel technology. Continuing its support of the Intel Foundry Accelerator Alliance Program, Cadence has joined the Intel Foundry Chiplet Alliance Program as a founding member to ensure its solutions will help provide an assured and scalable path for customers looking to deploy designs that leverage interoperable and secure chiplet solutions for targeted applications and markets. Cadence is already a participating member in the EDA, IP, Design Services and USMAG Alliances. "Cadence is at the forefront of facilitating next-generation AI, HPC and mobility designs with Intel 18A and 18A-P technologies, and our collaboration ensures that our mutual customers can leverage our robust design IP and AI-driven digital and analog/custom solutions for unparalleled performance and efficiency," said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. "Our expanded design IP portfolio for Intel Foundry builds on our commitment to delivering best-in-class silicon solutions, and our advanced implementations of leading standards are key to achieving scalable, high-performance designs. We look forward to continuing to partner with Intel Foundry to build out IP solutions for the AI factories and compute platform needs of the future as well as today." "As we optimize solutions through our ongoing collaboration, the combination of Cadence's innovative IP solutions and Intel 18A and 18A-P technologies delivers advantages for AI/ML and HPC applications," stated Suk Lee, vice president and general manager, Ecosystem Technology Office at Intel Foundry. "Working together, we are accelerating the development of high-performance solutions, including for chiplets, that meet the evolving needs of the industry and empower our mutual customers to drive PPA efficiencies and accelerate time to market for their innovative next-generation SoC designs." For more information about Cadence and its collaboration with Intel Foundry, please visit the Intel Foundry partner webpage. About Cadence Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence's Intelligent System Design™ strategy, are essential for the world's leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world's top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at © 2025 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at are trademarks or registered trademarks of Cadence Design Systems, Inc. MIPI and SoundWire are registered trademarks owned by MIPI Alliance. PCI Express and PCIe are registered trademarks of PCI-SIG. Universal Chiplet Interconnect Express and UCIe are trademarks of UCIe Consortium. All other trademarks are the property of their respective owners. Category: Featured View source version on Contacts For more information, please contact: Cadence Newsroom408-944-7039newsroom@ Sign in to access your portfolio

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