Latest news with #FinFET
Yahoo
16-05-2025
- Science
- Yahoo
Chinese Researchers Say They Have a Fast, Silicon-Free Transistor
A team of researchers from Peking University claims to have developed a non-silicon transistor that is faster and more power-efficient than the latest tech in the industry. If the claim, which is published in the journal Nature Materials (out of London), is accurate, it would mean that China has bleeding-edge tech that could rival chips from Intel and TSMC, among others. Still, it's a long way from publishing a research paper to turning the tech industry on its head. The team developed a two-dimensional transistor using bismuth oxyselenide. The team's transistor has Gate-all-around technology, the latest field-effect transistor technology. It replaces FinFET. Because GAAFET means less current leakage and helps chip makers create ever-smaller transistors, the inclusion of GAA in the research team's silicon-alternative efforts is crucial. Although the 2D bismuth transistor tech can potentially be more sturdy than silicon, the biggest draw for China could be that it might be able to use equipment it already has to produce transistors on a large scale. Interestingly, the team says that it managed to test its own transistor tech against Intel, Samsung, and TSMC technology and that it performed better than all of them, according to Tom's Hardware. That's a bold claim to make, and we'll believe it when we see it. Even before China and the US became embroiled in the Trump administration's tariffs, the US took steps to prevent China from getting its hands on the latest technology, including silicon transistors. In the face of these roadblocks, China has looked for ways to compete with the world's cutting-edge tech with different materials and home-brewed software. One of the more surprising examples of its occasional success is DeepSeek, which splashed onto the large language model (LLM) AI scene and battered Nvidia's stock (for a time). The fear with technology from China is that the country will use it to collect data on foreign states and their citizens. DeepSeek, for example, appears to be sending user data to China. Huawei, which is based in China, has been looking for ways to produce better processors, but has been challenged by roadblocks put up by the US. Although the research team doesn't indicate that Huawei has shown interest in its new transistor tech, it wouldn't be surprising if Huawei and others use it as a way to work around the limitations of their aging lithography machines.
Express Tribune
12-05-2025
- Science
- Express Tribune
Chinese researchers develop silicon-free transistor technology faster outpacing Intel, TSMC, and Samsung
Chinese researchers at Peking University have unveiled a potentially game-changing silicon-free transistor, claiming it could outperform the latest chips from Intel, TSMC, and Samsung. The innovation, based on a two-dimensional material known as bismuth oxyselenide, marks a major shift in chip architecture. The transistor employs a gate-all-around (GAAFET) design, with the gate fully enveloping the source—unlike traditional FinFET technology, which provides only partial gate coverage. This full-contact structure significantly reduces energy leakage and allows greater control over current flow, resulting in improved performance. According to the research team, the new transistor operates up to 40% faster than Intel's latest 3nm chips and consumes 10% less power. Tests were conducted under the same conditions used for commercial-grade processors. The findings, published in Nature Materials, suggest the transistor may represent the most efficient and powerful to date. Lead scientist Professor Peng Hailin described the innovation as 'changing lanes' rather than simply improving existing materials. The new design avoids the vertical stack typical of FinFETs and instead resembles an interwoven bridge-like structure, helping overcome miniaturisation challenges as chip sizes approach sub-3nm levels. Two novel bismuth-based compounds power the breakthrough: Bi₂O₂Se as the semiconductor and Bi₂SeO₅ as the gate dielectric. Both materials feature low interface energy, reducing electron scattering and enabling near-resistance-free electron flow. 'This allows electrons to flow with almost no resistance, like water through a smooth pipe,' Peng explained. Importantly, the researchers say their transistor can be fabricated using existing semiconductor infrastructure, potentially easing the path to large-scale production. They have already used the design to create small logic units. If commercialised, the development could significantly disrupt the global chip market and accelerate the shift away from silicon-based technology.
Yahoo
08-05-2025
- Automotive
- Yahoo
NXP Unveils Next-Gen Radar Chip To Boost Autonomous Driving Systems
NXP Semiconductors NV (NASDAQ:NXPI) showcased its new S32R47 imaging radar processors in 16 nm FinFET technology on Thursday. The third generation of imaging radar processors delivers up to twice the processing power of the previous generation. With NXP's mmWave radar transceivers, power management, and in-vehicle networking solutions, the S32R47 family meets functional safety ASIL ISO 26262 ASIL B(D) requirements. Also Read: According to Yole Intelligence's Status of the Radar Industry 2024 report, by 2029, approximately 40% of vehicles entering the road will be passenger cars with driving automation Level 2+(L2+)/ Level 3 (L3), with an increasing number of vehicles with Level 4 (L4). Imaging radar leverages richer point cloud data for more detailed modeling of the environment. This is a key enabler for AI-based perception systems, which allow for assisted and autonomous driving in the most challenging environmental conditions, such as complex urban scenarios. The S32R47 integrates a high-performance multi-core radar processing system, allowing denser point cloud output and enhanced algorithms that enable next-generation ADAS systems. This results in better separability of objects, improved detection reliability, and more accurate classification of objects such as vulnerable road users or lost cargo. In April, NXP reported first-quarter results. The company reported first-quarter revenue of $2.84 billion, down 9%, in line with analyst estimates. The company reported first-quarter adjusted earnings of $2.64 per share, beating analyst estimates of $2.58. NXP expects second-quarter revenue of $2.8 billion to $3 billion versus estimates of $2.87 billion. The company sees second-quarter adjusted earnings of $2.46 to $2.86 per share versus estimates of $2.65. "NXP's first-quarter results and guidance for the second quarter underpin a cautious optimism that NXP continues to effectively navigate through a challenging set of market conditions. We are operating in a very uncertain environment influenced by tariffs with volatile direct and indirect effects," said Kurt Sievers, president and CEO of NXP. "Considering these external factors, we are redoubling our efforts to manage what is in our direct control, enabling NXP to drive solid profitability and earnings," Sievers added. Price Action: NXPI stock is trading up 0.97% to $188.69 at the last check on Thursday. Image via Shutterstock Up Next: Transform your trading with Benzinga Edge's one-of-a-kind market trade ideas and tools. Click now to access unique insights that can set you ahead in today's competitive market. Get the latest stock analysis from Benzinga? This article NXP Unveils Next-Gen Radar Chip To Boost Autonomous Driving Systems originally appeared on © 2025 Benzinga does not provide investment advice. All rights reserved. Error in retrieving data Sign in to access your portfolio Error in retrieving data Error in retrieving data Error in retrieving data Error in retrieving data
Time of India
08-05-2025
- Automotive
- Time of India
NXP introduces third-generation imaging radar processors for advanced autonomous driving
NXP Semiconductors has introduced its S32R47 imaging radar processors , utilising 16 nm FinFET technology, to enhance autonomous driving capabilities. The third-generation processors, building on NXP 's radar expertise, offer twice the processing power with improved cost and power efficiency. These processors, combined with NXP's other solutions, meet safety standards and aim to advance autonomous driving. The new S32R47 processors address the growing demand for autonomous driving technology . They are essential for features like piloted driving and automated parking . 'The S32R47 can efficiently process three times, or more, antenna channels in real time than today's production solutions. It enables improved imaging radar resolution, sensitivity and dynamic range - required by demanding autonomous driving use cases - while still meeting the stringent power and system cost targets set by OEMs for volume production', said Meindert van den Beld, Senior Vice President & General Manager, Radar & ADAS.
Yahoo
06-05-2025
- Yahoo
Arrow Lake die shot shows off the details of Intel's chiplet-based design
When you buy through links on our articles, Future and its syndication partners may earn a commission. Credit: Intel Die shots of Intel's Arrow Lake architecture have been published, revealing Intel's chiplet (tile) infused design in all of its glory. Andreas Schiling on X shared several images of Arrow Lake up close, revealing the layout of Arrow Lake's individual tiles and the layout of the cores inside the compute tile. The first photo exposes the full die of Intel's desktop Core Ultra 200S series CPUs, with the compute tile on the upper left, the IO tile on the bottom, and the SoC tile and GPU tile on the right. To the bottom left and top right are two filler dies designed to provide structural rigidity. The compute die is fabbed on TSMC's bleeding-edge N3B node, with a total area of 117.241 mm². The IO tile and SoC tile are fabbed on TSMC's older N6 node, with the IO tile measuring 24.475mm squared and the SoC tile 86.648mm squared. All of the tiles rest on an underlying base tile fabbed on Intel's 22nm FinFET node. Arrow Lake is the first Intel architecture that is fabricated entirely using nodes from a competitor, except for the base tile. The next image shows all of the sub-components for the secondary tiles in Arrow Lake. The I/O die houses the Thunderbolt 4 controller/display PHY, PCIe Express buffers/PHYs, and TBT4 PHYs. The SoC tile houses the display engines, media engine, more PCIe PHYs, buffers, and the DDR5 memory controllers. The GPU tile houses four Xe GPU cores and an Xe LPG (Arc Alchemist) render slice. The final image shows off Intel's latest core configuration for Arrow Lake, which differs from previous hybrid Intel architectures. For Arrow Lake, Intel opted to sandwich the E-cores between the P-cores rather than putting them all in their own cluster, allegedly to reduce thermal hotspots. Four of the eight P-cores reside on the borders of the die with the other four residing in the middle of the die. The four E-core clusters (which house four cores each) are sandwiched between the outer and inner P-cores. Schilling's die shot also exposes the cache layout for Arrow Lake, comprised of 3MB of L3 cache per P-core (36MB in total) and 3MB of L2 cache per E-core cluster, with 1.5MB shared between two cores directly. An interconnect bridges the two L2 cache clusters (and their associated cores) together, which is also responsible for connecting each core cluster to the ring agent. One major upgrade Intel made with Arrow Lake is connecting the E-core clusters to L3 cache shared by the P-cores, effectively giving the E-cores an L3 cache. Arrow Lake is one of Intel's most complex architectures to date and the first from the company to bring a chiplet-style design to the desktop market. That said, Intel's first attempt at a desktop chiplet-based competitor has not been well received, due to latency issues from the interconnect, which is responsible for connecting all the tiles together. Intel is attempting to rectify the issue through firmware updates. Still, its current implementation can't touch AMD's competing Ryzen 9000 CPUs (such as the 9800X3D), nor is it enough to even beat its own previous-generation 14th-generation processors in gaming (such as the 14900K). All that said, moving to a chiplet approach will afford Intel more ways to optimize its architectures down the road, in a more efficient manner. Each tile can be developed independently of others and built with different nodes to improve yields, optimize development, and reduce production costs.
