Latest news with #JEDEC
Associated Press
4 days ago
- Business
- Associated Press
MIPI Alliance Releases I3C Basic v1.2 Utility and Control Bus Interface for Mobile, IoT and Data Center Applications
BRIDGEWATER, N.J.--(BUSINESS WIRE)--Aug 6, 2025-- The MIPI Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, today announced the release of MIPI I3C Basic v1.2, a scalable utility and control bus interface for connecting peripherals to a microcontroller or an application processor, streamlining integration and improving cost efficiencies. Version 1.2 reorganizes the specification, with separate sections for mandatory and optional features that can be implemented based on application needs. This press release features multimedia. View the full release here: MIPI I3C Basic is a rich subset of the member-version MIPI I3C that is licensed on royalty-free terms. The I3C interface, introduced in 2016 and significantly updated to v1.1 in 2019, was designed to build upon the key attributes of the legacy serial interfaces I2C, SPI and UART while making it easier to implement. At the same time, it offers greater performance and power efficiency, and adds a host of features that remove many of the pain points faced by developers. MIPI I3C Basic has also been the centerpiece of several industry collaborations. It has been adopted by PCI-SIG and NVM Express as a system management bus (SMBus), by JEDEC in its sideband bus and DDR5 standard, by ETSI in its Smart Secure Platform (SSP) and Universal Integrated Circuit Card (UICC), and is an area of focus for a MIPI liaison relationship with DMTF (Distributed Management Task Force). Users may download the I3C Basic specification on the MIPI website. Key use cases include: The I3C product ecosystem includes microcontrollers, microprocessing units, wireless IoT SoCs (systems on chips), sensors and specialty integrated circuits. A large set of tools is also available to support development and testing—from protocol analyzers to development boards to USB host adapters. Software drivers are available for Linux and the Zephyr real-time OS, and companies have provided reference implementations for their specific products. MIPI member companies integrating MIPI I3C into their products and services include: Binho LLC; Boréas Technologies Inc.; Diodes Incorporated; Microchip Technology; Montage Technology Co., Ltd.; NXP ® Semiconductors; Prodigy Technovations Pvt. Ltd.; Renesas Electronics Corporation; Robert Bosch GmbH; SmartDV Technologies India Private Limited; STMicroelectronics; Synopsys, Inc.; TDK InvenSense; Teledyne LeCroy; Texas Instruments Incorporated and others. 'The MIPI I3C ecosystem has grown rapidly over the past few years, and we expect this rapid adoption to persist,' said Hezi Saar, chair of MIPI Alliance. 'Companies have embraced the I3C interface for its innovative features and substantial improvements in performance and power efficiency compared with legacy interfaces. I3C offers developers exceptional flexibility, making it suitable for a diverse range of products, from smartphones and wearables to data center systems.' To keep up with MIPI Alliance, subscribe to the MIPI blog and stay connected by following MIPI on LinkedIn, X and YouTube. MIPI® and I3C® are registered trademarks owned by MIPI Alliance. I3C Basic™, Debug Over I3C™, DisCo™ for I3C, I3C HCI™ and I3C TCRI™ are trademarks owned by MIPI Alliance. View source version on CONTACT: Press Contact:Lisa McCausland Geneva Street Marketing for MIPI Alliance +1 303.888.2137 [email protected] KEYWORD: UNITED STATES NORTH AMERICA NEW JERSEY INDUSTRY KEYWORD: DATA MANAGEMENT AUTOMOTIVE MANUFACTURING TECHNOLOGY MANUFACTURING IOT (INTERNET OF THINGS) WEARABLES/MOBILE TECHNOLOGY SEMICONDUCTOR APPS/APPLICATIONS SOFTWARE MOBILE/WIRELESS HARDWARE SOURCE: MIPI Alliance Copyright Business Wire 2025. PUB: 08/06/2025 09:13 AM/DISC: 08/06/2025 09:12 AM
Business Wire
22-07-2025
- Business
- Business Wire
Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC's 22ULP and 14FFC
HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design and IP provider, today announced the availability of its DDR/LPDDR combo PHY, supporting from 3 rd to 5 th -generation on UMC's 22ULP and 14FFC platforms, which are UMC's planar and FinFET process technologies. Faraday continues its long-standing commitment to delivering in-house IP solutions optimized to better serve the ASIC market. Faraday's DDR/LPDDR combo IP solution helps accelerate design cycles, reduce development risks, and deliver high-quality, reliable memory subsystems. Share Faraday's DDR/LPDDR IP solutions feature robust, silicon-proven designs widely adopted in ASIC projects across diverse SoC applications. Full compliance with JEDEC specifications ensures seamless compatibility and allows for flexible performance and power optimization. The 22ULP PHY supports low operating voltage at 0.8V, making it ideal for power-sensitive applications such as mobile, 5G, and IoT devices. The 14nm PHY supports transmission rate up to 6400Mbps for DDR5/LPDDR5 and includes advanced features such as self-training mechanisms, impedance calibration, and DFE. 'Our customers demand high performance and low power in increasingly complex SoCs,' said Flash Lin, COO of Faraday. 'With the complete DDR/LPDDR IP solution spanning controller, PHY, and subsystem integration, we're helping customers accelerate design cycles, reduce development risks, and deliver high-quality, reliable memory subsystems.' About Faraday Technology Corporation Faraday Technology Corporation (TWSE: 3035) is dedicated to the mission of benefiting humanity and upholding sustainable values in every IC it handles. The company offers a comprehensive range of ASIC solutions, including 2.5D/3D Advanced packaging, Arm Cortex-A, R, M, A720AE, Neoverse CSS integration and hardening, FPGA-Go-ASIC, and design implementation services. Furthermore, its extensive silicon IP portfolio encompasses a wide array of offerings, such as I/O, Cell Library, Memory Compiler, DDR/LPDDR, MIPI D-PHY, V-by-One, USB, Giga Ethernet, SATA, PCIe, and SerDes. For further information, visit or follow Faraday on LinkedIn.
Yahoo
14-07-2025
- Business
- Yahoo
CDNS Unveils LPDDR6/5X Memory IP System for Next-Gen AI & HPC Workload
Cadence Design Systems (CDNS) recently announced the tapeout of the industry's first LPDDR6/5X memory IP system solution, capable of operating at an impressive 14.4Gbps—a 50% speed boost over previous LPDDR generations. The state-of-the-art IP system not only advances the frontiers of AI infrastructure but also caters to high-performance computing (HPC), data centers and mobile applications by enabling faster data movement, lower latency and scalable integration options. The Cadence IP for the JEDEC LPDDR6/5X standard features a sophisticated PHY architecture combined with a high-performance controller, optimized to deliver exceptional power, performance and area (PPA) efficiency. It provides comprehensive support for both LPDDR6 and LPDDR5X DRAM protocols, ensuring maximum design flexibility. This solution seamlessly integrates into conventional monolithic SoCs as well as advanced multi-die systems by leveraging the Cadence chiplet framework. Notably, this framework, built on the success of the previous LPDDR generation, was successfully taped out in 2024, highlighting its viability for heterogeneous chiplet integration. The integrated PHY and controller memory solution features a cutting-edge, high-performance architecture that is both scalable and adaptable, building on Cadence's well-established DDR5 (12.8Gbps), LPDDR5X (10.7Gbps) and GDDR7 (36G) product lines. As the inaugural release in Cadence's new LPDDR6 IP portfolio, this offering provides full support for the LPDDR6 and LPDDR5X standards, including compatibility with LPDDR5X CAMM2, ensuring robust performance and broad applicability. Designed to serve diverse markets including AI, mobile, consumer electronics, enterprise HPC, and cloud data centers, this advanced LPDDR6/5X memory IP solution delivers improved flexibility to meet varying performance, capacity and cost requirements, supporting extended product lifecycles. The LPDDR6/5X PHY can be tailored to different package and system configurations and is offered as a drop-in hardened macro. This enables quick, reliable integration, significantly accelerating time-to-market for end products. The Cadence LPDDR6/5X controller offers a comprehensive suite of standard and advanced features for memory interfaces, including compatibility with the Arm AMBA AXI bus. Delivered as a soft RTL macro, the controller provides designers with maximum flexibility to optimize features, power, area and performance to suit their specific application needs. Cadence extends its solutions beyond silicon by offering a comprehensive LPDDR6 Memory Model. This model enables engineering teams to conduct thorough protocol checks, achieve functional coverage and follow a defined verification plan to ensure JEDEC compliance. This helps reduce the verification burden on system designers and accelerates the time-to-market for next-generation SoCs adopting LPDDR6. Additionally, this LPDDR6/5X memory IP is part of Cadence's extensive memory IP suite, which also offers DDR, GDDR and HBM technologies. When combined with Cadence's leading analog/mixed-signal tools and UCIe-based chiplet frameworks, customers can develop complete systems with optimized performance and faster time-to-market. Cadence's performance is being boosted by solid demand and intense design activity. Long-term trends such as 5G growth, the rapid rise of hyperscale computing and advancements in autonomous driving are driving increased design work throughout the semiconductor industry. In June 2025, it announced a major expansion of its partnership with Samsung Foundry through a new multi-year IP agreement. This collaboration aims to expand Cadence's portfolio of memory and interface IP solutions across Samsung's advanced process technologies, including SF4X, SF5A and SF2P nodes. By combining CDNS' AI-driven design platforms with Samsung's cutting-edge fabrication technologies, the two companies are set to deliver high-performance, low-power solutions tailored for AI data centers, automotive applications such as ADAS and next-generation RF connectivity. However, the company is up against strong competition from other EDA firms such as Synopsys, ANSYS and Siemens AG (after it acquired Mentor Graphics). This rising competitive intensity puts downward pressure on pricing, squeezing margins. To maintain its edge, Cadence has ramped up its R&D investments, especially in verification and digital design tools, which, while necessary, may hinder operating margin growth. CDNS currently has a Zacks Rank #2 (Buy). Shares of the company have soared 21.3% in the past three months compared with the Zacks Computer-Software industry's growth of 29.8%. Image Source: Zacks Investment Research Some other top-ranked stocks from the broader technology space are NETGEAR, Inc. (NTGR), TaskUs, Inc. (TASK) and Cognizant Technology Solutions Corporation (CTSH). NTGR currently sports a Zacks Rank #1 (Strong Buy), and TASK and CTSH carry a Zacks Rank #2. You can see the complete list of today's Zacks #1 Rank stocks here NETGEAR's earnings beat the Zacks Consensus Estimate in each of the trailing four quarters, with the average surprise being 179.12%. In the last reported quarter, NTGR delivered an earnings surprise of 105.71%. Its shares have gained 92.6% in the past year. TaskUs' earnings beat the Zacks Consensus Estimate in two of the trailing four quarters, matched in one and missed in the other, with the average surprise being 6.39%. In the last reported quarter, TASK delivered an earnings surprise of 18.75%. Its shares have risen 7% in the past year. Cognizant's earnings beat the Zacks Consensus Estimate in the trailing four quarters, the average surprise being 6.38%. In the last reported quarter, CTSH delivered an earnings surprise of 3.36%. Its shares have grown 4% in the past year. Want the latest recommendations from Zacks Investment Research? Today, you can download 7 Best Stocks for the Next 30 Days. Click to get this free report Cognizant Technology Solutions Corporation (CTSH) : Free Stock Analysis Report NETGEAR, Inc. (NTGR) : Free Stock Analysis Report Cadence Design Systems, Inc. (CDNS) : Free Stock Analysis Report TaskUs, Inc. (TASK) : Free Stock Analysis Report This article originally published on Zacks Investment Research ( Zacks Investment Research Error in retrieving data Sign in to access your portfolio Error in retrieving data Error in retrieving data Error in retrieving data Error in retrieving data
Business Wire
09-07-2025
- Business
- Business Wire
Cadence Introduces Industry-First LPDDR6/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure
SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced the tapeout of the industry's first LPDDR6/5X memory IP system solution optimized to operate at 14.4Gbps, up to 50% faster than the previous generation of LPDDR DRAM. The new Cadence ® LPDDR6/5X memory IP system solution is a key enabler for scaling up the AI infrastructure to accommodate the memory bandwidth and capacity demands of next-generation AI LLMs, agentic AI and other compute-heavy workloads for various verticals. Multiple engagements are currently underway with leading AI, high-performance computing (HPC) and data center customers. The evolution of data centers from HPC compute virtualization to AI training and inference at scale has driven a massive buildout of AI infrastructure, and designing for efficient data movement via memory interfaces has never been more crucial. Share The Cadence IP for the JEDEC LPDDR6/5X standard consists of an advanced PHY architecture and a high-performance controller designed to maximize power, performance and area (PPA) while supporting both LPDDR6 and LPDDR5X DRAM protocols for optimal flexibility. The solution supports native integration into traditional monolithic SoCs as well as multi-die system architectures by leveraging the Cadence chiplet framework, enabling heterogeneous chiplet integration. The chiplet framework, including the previous LPDDR generation, was successfully taped out in 2024. 'The evolution of data centers from HPC compute virtualization to AI training and inference at scale has driven a massive buildout of AI infrastructure, and designing for efficient data movement via memory interfaces has never been more crucial. LPDDR6 has emerged as a key enabler of accelerated compute, providing the speed, bandwidth, power profile and capacity needed to efficiently perform AI inference,' said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. 'With this tapeout, Cadence is continuing our track record of memory IP leadership by offering an industry-first LPDDR6 implementation delivered as an integrated subsystem optimized for customer applications.' The complete PHY and controller memory system boasts a new high-performance, scalable and adaptable architecture based on Cadence's proven and highly successful DDR5 12.8Gbps, LPDDR5X 10.7Gbps and GDDR7-36G product lines. This first offering in Cadence's new LPDDR6 IP product line supports the LPDDR6 and LPDDR5X standards, including LPDDR5X CAMM2. Suitable for the AI, mobile, consumer, enterprise HPC and cloud data center markets, the advanced LPDDR6/5X memory IP system solution allows maximum flexibility for end products with a range of performance, capacity and cost targets—ensuring long production runs. The LPDDR6/5X PHY is customizable for different package and system topologies and available as a drop-in hardened macro. This ensures fast and reliable integration, translating into rapid time to market. The Cadence LPDDR6/5X controller includes a full set of industry-standard and advanced features for memory interfaces, such as support for the Arm ® AMBA ® AXI bus. The memory controller is provided as a soft RTL macro for maximum flexibility in features, power, area and performance. The Cadence LPDDR6 solution includes the LPDDR6 Memory Model, which enables engineers to perform comprehensive verification and ensure that system-on-chip (SoC) designs are compatible with the latest JEDEC interface standard, accelerating their adoption of this new technology with confidence. The LPDDR6 Memory Model includes a complete set of protocol checks, functional coverage and a verification plan. Available now for customer engagements, the new LPDDR6/5X IP is the latest addition to Cadence's comprehensive family of memory IP system solutions, which also includes DDR, GDDR and HBM. Cadence Memory IP is designed with the company's industry-leading analog/mixed-signal design tools. When combined with Cadence's UCIe ™ -based chiplet framework, the new LPDDR6/5X IP and Cadence's other leading memory and interface IP deliver an optimized solution that enables rapid chiplet realization. For more information on the new LPDDR6/5X IP, please visit the LPDDR landing page on About Cadence Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence's Intelligent System Design ™ strategy, are essential for the world's leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world's top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at © 2025 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at are trademarks or registered trademarks of Cadence Design Systems, Inc. Arm and AMBA are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. UCIe is a trademark of UCIe Consortium. All other trademarks are the property of their respective owners. Category: Featured
Yahoo
22-05-2025
- Automotive
- Yahoo
Navitas Redefines Reliability with Industry's First Automotive ‘AEC-Plus' Qualified SiC MOSFETs in HV-T2Pak Top-Side Cooled Package
Unprecedented reliability combined with superior performance & optimized, high-creepage package sets a new benchmark in automotive and industrial applications Navitas Redefines Reliability with Industry's First Automotive 'AEC-Plus' Qualified SiC MOSFETs in HV-T2Pak Top-Side Cooled Package TORRANCE, Calif., May 05, 2025 (GLOBE NEWSWIRE) -- Navitas Semiconductor (Nasdaq: NVTS), the only pure-play, next-generation power semiconductor company and industry leader in gallium nitride (GaN) power ICs and silicon carbide (SiC) technology, introduces a new level of reliability to meet the system lifetime requirements of the most demanding automotive and industrial applications. Navitas' latest generation of 650 V and 1200 V 'trench-assisted planar' SiC MOSFETs combined with an optimized, HV-T2Pak top-side cooled package, delivers the industry's highest creepage of 6.45 mm to meet IEC-compliance for applications up to 1200V. Navitas' HV-T2Pak SiC MOSFETs significantly increase system-level power density and efficiency while improving thermal management and simplifying board-level design and manufacturability. Target applications include EV on-board chargers (OBC) & DC-DC converters, data-center power supplies, residential solar inverters & energy storage systems (ESS), EV DC fast chargers, and HVAC motor drives. AEC-Q101 is an automotive industry standard developed by the Automotive Electronics Council (AEC) to establish common part-qualification and quality-system standards. Navitas has created an industry-first benchmark, 'AEC-Plus'*, indicating parts qualified above and beyond the existing AEC-Q101 and JEDEC product qualification standards. This new benchmark showcases Navitas' deep understanding of system-level lifetime requirements and a strong commitment to enabling rigorously designed and validated products for demanding mission profiles in automotive and industrial applications. The 'AEC-Plus' qualification standards extend further into rigorous multi-lot testing and qualification. Key additions to the existing AEC-Q101 requirements include: Dynamic reverse bias (D-HTRB) & dynamic gate switching (D-HTGB) to represent stringent application mission profiles Over 2x longer power & temperature cycling Over 3x longer duration for static high-temperature, high-voltage tests (e.g. HTRB, HTGB) 200°C TJMAX qualification for overload operation capability Navitas' HV-T2Pak top-side cooled package, in an industry-standard compact form factor (14 mm x 18.5 mm), is optimized with an innovative groove design in the package mold compound that extends the creepage to 6.45 mm without reducing the size of the exposed thermal pad and ensuring optimal heat dissipation. In addition, the exposed thermal pad has a nickel, nickel-phosphorus (NiNiP) plating, as opposed to tin (Sn) plating from existing TSC package solutions, which is critical to preserving the post-reflow surface planarity of the exposed pad and ensuring thermally efficient and reliable attachment to the thermal interface material (TIM). Enabled by over 20 years of SiC technology innovation leadership, Navitas' GeneSiC™ 'trench-assisted planar SiC MOSFET technology' offers up to 20% lower on-resistance under in-circuit operation at high temperatures compared to competition and superior switching figure-of-merits which result in the lowest power losses across a wider operating range. All GeneSiC™ SiC MOSFETs have the highest-published 100%-tested avalanche capability, excellent short-circuit withstand energy, and tight threshold voltage distributions for easy paralleling. The initial HV-T2Pak portfolio includes 1200 V SiC MOSFETs with on-resistance ratings ranging from 18 mΩ to 135 mΩ and 650 V SiC MOSFETs with on-resistance ratings ranging from 20 mΩ to 55 mΩ. Lower on-resistance (<15 mΩ) SiC MOSFETs in HV-T2Pak package will be announced later in 2025. For more information, please contact info@ or visit *Navitas uses the term 'AEC-Plus' to indicate parts exceeding AEC-Q101 standards for reliability testing, published by the Automotive Electronics Council (AEC), based on Navitas test results About NavitasNavitas Semiconductor (Nasdaq: NVTS) is the only pure-play, next-generation power-semiconductor company, celebrating 10 years of power innovation founded in 2014. GaNFast™ power ICs integrate gallium nitride (GaN) power and drive, with control, sensing, and protection to enable faster charging, higher power density, and greater energy savings. Complementary GeneSiC™ power devices are optimized high-power, high-voltage, and high-reliability silicon carbide (SiC) solutions. Focus markets include AI data centers, EV, solar, energy storage, home appliance / industrial, mobile, and consumer. Over 300 Navitas patents are issued or pending, with the industry's first and only 20-year GaNFast warranty. Navitas was the world's first semiconductor company to be CarbonNeutral®-certified. Navitas Semiconductor, GaNFast, GaNSense, GeneSiC, and the Navitas logo are trademarks or registered trademarks of Navitas Semiconductor Limited and affiliates. All other brands, product names, and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Contact InformationLlew Vaughan-Edmunds, Sr Director, Product Management & Marketing info@ Photos accompanying this announcement are available at: in to access your portfolio
