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Nokia, Nvidia, defence firms back EU-funded drone infrastructure oversight project
Nokia, Nvidia, defence firms back EU-funded drone infrastructure oversight project

Time of India

time2 days ago

  • Business
  • Time of India

Nokia, Nvidia, defence firms back EU-funded drone infrastructure oversight project

By Nathan Vifflin A consortium of more than 42 organizations, led by Nokia , will work on an unmanned drone project aimed at protecting and bolstering the resilience of Europe's most critical infrastructures, the Finnish network equipment maker said on Wednesday. The member organizations, which include start-ups and universities, will build new capabilities such as laser or radar sensors on top of hardware platforms like drones built by defence companies. Russia's invasion of Ukraine has highlighted the European Union's inability to protect its vital systems, a vulnerability starkly underscored by drone warfare's increasing capacity to inflict devastation deep within adverse territory. "Safeguarding of our critical infrastructure has not always been a first priority," project leader Thomas Eder at Nokia said in an interview with Reuters, adding that EU-funding for a similar venture did not come through only a few years earlier. The project is funded in part by participating countries, companies and the EU under its Chips Joint Undertaking programme, which also allows non-EU countries such as Israel to participate. Among companies involved in the venture were Nvidia and European defence firms Safran, Leonardo and Saab. Nokia is looking to do more around defence as its new CEO has identified the sector as one of the company's priority areas, alongside data centres and AI, a Nokia spokesperson said. The aerial, ground and underwater robot project, initially scheduled to run for three years, is expected to generate 90 million euros ($102.7 million) in revenue by 2035, according to a statement seen by Reuters. Nokia was not able to confirm the total funding numbers for the project. While the initiative is targeted for civil security, when asked if it could be later spun-off into a dual-use project for defence purposes, Eder said, "I think it is highly possible." "But for the time being, this is a critical infrastructure project for power lines, for power plants, for railways, for ports, for any type of power grid applications," he said.

TSMC to open chip design centre in Munich, could later support AI development
TSMC to open chip design centre in Munich, could later support AI development

Time of India

time28-05-2025

  • Automotive
  • Time of India

TSMC to open chip design centre in Munich, could later support AI development

By Nathan Vifflin AMSTERDAM: Taiwan Semiconductor Manufacturing Co, the world's largest contract chipmaker, said on Tuesday it will open a design centre in Munich, Germany, which could at a later date help develop chips via leading manufacturing processes for applications such as artificial intelligence. President of TSMC Europe, Paul de Bot, said at the company's 2025 Technology Symposium event that the Munich Design Centre would open during the third quarter of 2025. "It's intended to support European customers in designing high-density, high-performance, and energy-efficient chips with a focus on applications again in automotive, industrial, AI, and IoT," de Bot said. Europe is currently formulating a strategy to catch up with the U.S. and China on artificial intelligence. TSMC is building together with Infineon , NXP and Robert Bosch a new 10 billion euro ($11.33 billion) microchip manufacturing plant in Dresden, Germany, through a joint venture called European Semiconductor Manufacturing Co (ESMC). When asked if ESMC or the design center could assist in meeting Europe's AI chips ambitions at a later stage, executive Kevin Zhang said TSMC has engaged conversations with its partners. "I'm all for building up the most semiconductor capability in Europe for AI applications... This design center obviously potentially can be leveraged to bring the leading node support," Zhang said in a press briefing with journalists, referring to advanced processes used to make AI chips, among others. The Munich centre will work on all ESMC nodes, not exclusively depending on the future customer base, he said. TSMC joins its largest customer in the Bavarian capital, Apple, which has invested 2 billion euros to build its largest engineering hub in Europe there. Dresden-based ESMC aims to manufacture chips using smaller manufacturing technology previously unavailable at European chipmakers like Infineon, STMicroelectronics, or NXP. "We have to be on the ground right here closer. We need to have people here to really directly engage with customers," Zhang added.

TSMC still evaluating ASML's 'High-NA' as Intel eyes future use
TSMC still evaluating ASML's 'High-NA' as Intel eyes future use

Time of India

time28-05-2025

  • Business
  • Time of India

TSMC still evaluating ASML's 'High-NA' as Intel eyes future use

By Nathan Vifflin AMSTERDAM: Taiwan Semiconductor Manufacturing Co., the world's largest contract chipmaker, is still assessing when it will use ASML's cutting-edge high numerical aperture (NA) machines for its future process nodes, an executive said on Tuesday. Chipmakers are weighing when the speed and accuracy benefits of these nearly $400 million machines will outweigh the almost doubled price tag of what is already the most expensive piece of equipment in a chip fabrication plant. Asked if TSMC plans to use the machine for its upcoming A14, and enhanced versions of the future node, Kevin Zhang said the company hasn't yet found a compelling reason. "A14, the enhancement I talk about, is very substantial without using High-NA. So our technology team continues to find a way to extend the life of current ( Low-NA EUV machines ) by harvesting the scaling benefit," he said at a press briefing. "As long as they continue to find a way, obviously we don't have to use it," Zhang said. Rival Intel has planned to use the High-NA EUV machine in its future manufacturing process, known as 14A, in an attempt to revive its contract chip business and better compete with TSMC. However, Intel also says that customers will still have the option of using older and more proven technologies. During ASML's last earnings report, CEO Christophe Fouquet said he expects customers to test High-NA for high-volume manufacturing readiness through 2026-2027, before they evaluate the tool on their most advanced nodes in a latter phase. Last year, Zhang had told reporters TSMC will not use High-NA for its A16 node, adding he did not like the sticker price. So far, ASML has shipped five of the 180 ton, double-decker sized machine across the world to three customers, counting Intel, TSMC and Samsung.

TSMC still evaluating ASML's 'High-NA' as Intel eyes future use
TSMC still evaluating ASML's 'High-NA' as Intel eyes future use

Yahoo

time27-05-2025

  • Business
  • Yahoo

TSMC still evaluating ASML's 'High-NA' as Intel eyes future use

By Nathan Vifflin AMSTERDAM (Reuters) -Taiwan Semiconductor Manufacturing Co ( the world's largest contract chipmaker, is still assessing when it will use ASML's cutting-edge high numerical aperture (NA) machines for its future process nodes, an executive said on Tuesday. Chipmakers are weighing when the speed and accuracy benefits of these nearly $400 million machines will outweigh the almost doubled price tag of what is already the most expensive piece of equipment in a chip fabrication plant. Asked if TSMC plans to use the machine for its upcoming A14, and enhanced versions of the future node, Kevin Zhang said the company hasn't yet found a compelling reason. "A14, the enhancement I talk about, is very substantial without using High-NA. So our technology team continues to find a way to extend the life of current (Low-NA EUV machines) by harvesting the scaling benefit," he said at a press briefing. "As long as they continue to find a way, obviously we don't have to use it," Zhang said. Rival Intel has planned to use the High-NA EUV machine in its future manufacturing process, known as 14A, in an attempt to revive its contract chip business and better compete with TSMC. However, Intel also says that customers will still have the option of using older and more proven technologies. During ASML's last earnings report, CEO Christophe Fouquet said he expects customers to test High-NA for high-volume manufacturing readiness through 2026-2027, before they evaluate the tool on their most advanced nodes in a latter phase. Last year, Zhang had told reporters TSMC will not use High-NA for its A16 node, adding he did not like the sticker price. So far, ASML has shipped five of the 180 ton, double-decker sized machine across the world to three customers, counting Intel, TSMC and Samsung. Error in retrieving data Sign in to access your portfolio Error in retrieving data Error in retrieving data Error in retrieving data Error in retrieving data

Top semiconductor lab imec eyes 'programmable' AI chips, CEO says
Top semiconductor lab imec eyes 'programmable' AI chips, CEO says

Yahoo

time19-05-2025

  • Business
  • Yahoo

Top semiconductor lab imec eyes 'programmable' AI chips, CEO says

By Nathan Vifflin AMSTERDAM (Reuters) -The CEO of imec, one of the world's top semiconductor R&D firms, has said the industry needs to steer towards reconfigurable chip architectures if it wants to avoid becoming a bottleneck for the future generations of artificial intelligence. Rapid AI algorithm innovation outpaces the current strategy of developing specific, raw-power-focused chips, leading to major drawbacks in energy, cost and hardware development speed, CEO Luc Van den hove said in a statement seen by Reuters ahead of its publication. "There is a huge inherent risk of stranded assets because by the time the AI hardware is finally ready, the fast-moving AI software community may have taken a different turn," he said. Some, like OpenAI, have taken the path of building custom chips to speed up innovation, a move Van den hove said was risky and uneconomical for most. The Interuniversity Microelectronics Centre (imec) pioneers many semiconductor breakthroughs that chipmakers like TSMC and Intel often widely adopt years down the line. As the AI industry moves beyond large language models to agentic AI and physical AI for medical or autonomous driving applications, Van den hove sees future chips regrouping all necessary capabilities into building blocks called supercells. "A network-on-chip will steer and reconfigure these supercells so they can be quickly adapted to the latest algorithm requirements," Van den hove said. This will require true three dimensional stacking, a manufacturing technique where layers of logic and memory silicon are bonded together, he added. Belgium-based imec was a significant contributor to the advancement and refinement of 3D stacking, a technology that will be featured in TSMC's A14 and Intel's 18A-PT future nodes. The research and development firm will hold its flagship conference, ITF World, on Tuesday and Wednesday in Antwerp, Belgium. Sign in to access your portfolio

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