Latest news with #RISC-V
Time of India
a day ago
- Business
- Time of India
RISC-V can open up locked CPU market: Ananant Systems
NEW DELHI: The RISC-V Instruction Set Architecture (ISA) has the potential to open the tightly locked central processing unit (CPU) architecture, enabling startups and companies to develop chips for various customised applications, said a senior executive of Ananant Systems . Currently, SoftBank-backed chipmaker Arm Holdings licenses its RISC (Reduced Instruction Set Computer) technology to chipmakers like MediaTek and Qualcomm, who then develop processors for smartphones and tablets, while Intel and AMD's x86 CISC (Complex Instruction Set Computer) architecture powers general-purpose laptops and personal computers. Open-source RISC promises to lower the cost of developing affordable chipsets for specialised applications, such as artificial intelligence (AI) inferencing and wireless signal processors, Chitranjan Singh, founder & CEO, Ananant Systems, told ETTelecom in an interview. 'For the last few decades, the CPU architecture has been closed, and there has been no open-source architecture suitable for some of the huge use cases. So, RISC-V is very fit for standalone microcontrollers and embedded applications,' he said. The Bengaluru-headquartered startup, with in-house intellectual property (IP), chip design , semiconductor products, software, and systems, said its digital signal processor (DSP) chip uses RISC-V. CISC processors come with a large instruction set with complex instructions that can perform multiple operations in a single cycle, compared to RISC, which has a smaller instruction set with simpler, more easily executed instructions, making the technology suitable for applications where high-performance, simplicity and efficiency are the main criteria. '...with RISC-V, we can efficiently add a co-processor with specialised instruction sets for particular use cases of wireless signal processing and AI inference,' Singh said. 'Given the adaptability of the architecture, our product will be suitable for other applications like small cell and private 5G.' READ MORE | Ananant Systems working with major local OEMs to develop BSNL's 5G chip But despite the potential of RISC-V, its uptake has been slow. The executive attributed this to a lack of software ecosystem, adding that it may take 10-20 years to build a sizeable software segment that can run on this architecture. The startup is developing a 5G fixed wireless access (FWA) chip, which it says offers more efficiency and cost-savings over the incumbents. It is in discussions with state-controlled Bharat Sanchar Nigam Limited 's ( BSNL ) vendors to this extent. The Ministry of Electronics and IT (MeitY) in 2022 had launched the Digital India RISC-V, or the DIR-V programme, to enable India to realise self-reliance in semiconductors and microprocessors. Rajeev Chandrasekhar, the then minister of state for electronics and IT, had said that RISC-V has emerged as a strong alternative to Arm and Intel x86 in the last 10 years, having no licensing encumbrances, enabling its adoption by "one and all in the semiconductor industry, at different complexity levels for various design purposes". Notably, IIT Madras and the Centre for Development of Advanced Computing (C-DAC) have already developed the SHAKTI Processor and the VEGA Processor, respectively, based on RISC-V.
Yahoo
3 days ago
- Business
- Yahoo
HPC Innovator Taps Aion Silicon for $12M RISC-V Accelerator Program
End-to-End ASIC Partnership to Accelerate Global Supercomputing Market with Open-Standard, Energy-Efficient Silicon READING, United Kingdom, May 28, 2025 /PRNewswire/ -- Aion Silicon (formerly Sondrel), a leading ASIC and SoC architecture partner, today announced it has secured a $12 million engagement to provide comprehensive design services for a confidential customer developing next-generation RISC-V–based accelerators for high-performance computing (HPC) and artificial intelligence (AI). The multi-year program leverages Aion Silicon's two decades of SoC expertise to help the customer introduce disruptive, energy-efficient processors that target the most compute-intensive workloads in data centers and scientific research worldwide. Under the agreement, Aion Silicon will deliver the full spectrum of design work—from RTL architecture and verification through Design for Test, physical implementation, and tape-out—on a bleeding edge node RISC-V platform. "The global HPC race demands accelerators that deliver extreme performance per watt," said Oliver Jones, CEO of Aion Silicon. "This project shows how our team can turn bold RISC-V architectures into manufacturable silicon that challenges the dominance of proprietary solutions." Engagement Details End-to-end expertise — Complete RTL architecture, verification, Design for Test, physical implementation, and tape-out on a bleeding edge node RISC-V platform On-site collaboration — A dedicated team of Aion Silicon engineers willwork alongside the customer's team to accelerate knowledge transfer and project velocity Standards-based innovation — Open instruction-set architecture and vector extensions eliminate proprietary lock-in and speed customization for AI and HPC workloads Market impact — Accelerators are expected to deliver industry-leading efficiency, challenging the dominance of legacy architectures in data-center and scientific computing Engineering work is under way, with additional hires planned through 2025 as the design moves toward tape-out and initial silicon. About Aion SiliconAion Silicon is a trusted partner in high-performance semiconductor design, specializing in advanced System-on-Chip (SoC) solutions—including tailored ASICs—for AI, automotive, HPC, 5G, networking, and other applications. Its full-service, high-touch engineering model with consultative project leadership guides customers from SoC architecture and IP selection through design, foundry tapeout, and volume production. With over 20 years of experience in SoC architecture, front-end and back-end services, Aion Silicon reduces technical and economic risk for customers, accelerating time-to-market, while optimizing for commercial success. As a foundry-neutral and IP-agnostic partner with hundreds of successful tapeouts, Aion Silicon leverages a world-class ecosystem to deliver tailored solutions that meet each customer's unique needs. To learn more, visit All registered trademarks and product identifiers belong to their respective corporate entities. Any other trademarks or product names referenced here are also owned exclusively by their relevant companies. Media Contact:Gary BirdAion Silicon+1.831.888.9011aion@ View original content: SOURCE Aion Silicon
Arabian Post
7 days ago
- Business
- Arabian Post
Red Hat and Rocky Linux Advance RISC-V Integration
Red Hat Enterprise Linux and Rocky Linux are accelerating efforts to support the RISC-V architecture, signalling a significant shift in the enterprise Linux landscape. This development reflects the growing momentum behind RISC-V, an open-source instruction set architecture that is reshaping hardware innovation amid challenges in traditional chip supply chains and rising demand for customisable, energy-efficient computing. Red Hat, a subsidiary of IBM and a dominant force in the enterprise Linux market, has publicly confirmed its roadmap for incorporating RISC-V support into future releases of Red Hat Enterprise Linux . Similarly, the community-driven Rocky Linux project, a popular downstream fork of RHEL designed to provide enterprise-grade stability, has also announced ongoing work to integrate RISC-V compatibility. These parallel initiatives demonstrate broad industry recognition of RISC-V's potential to disrupt conventional processor markets dominated by x86 and ARM architectures. RISC-V's open standard removes licensing costs and restrictions typically associated with proprietary CPU designs, encouraging a diverse ecosystem of chip manufacturers, academic researchers, and software developers. This flexibility allows companies to tailor processor designs for specific workloads, which is particularly appealing for embedded systems, Internet of Things devices, and edge computing applications. Both Red Hat and Rocky Linux see this as a critical advantage for future-proofing their operating systems and meeting evolving customer needs. ADVERTISEMENT The move to support RISC-V involves extensive technical adaptation, as much of the existing software stack has been optimised for x86-64 and ARM64 platforms. Red Hat's engineering teams have been collaborating with hardware vendors and the wider open-source community to ensure that core components of RHEL, including the kernel, system libraries, and security modules, perform efficiently on RISC-V hardware. The company's investment in this area underscores its commitment to maintaining leadership across diverse infrastructure environments, including cloud, on-premises, and hybrid deployments. Rocky Linux, founded in the wake of CentOS's shift away from its traditional model, has quickly gained traction among enterprises seeking stable, free alternatives to RHEL. Its embrace of RISC-V support aligns with its mission to offer a robust platform compatible with the latest computing technologies. Developers contributing to Rocky Linux have been porting essential packages and testing workloads on early RISC-V development boards, working to iron out architecture-specific bugs and ensure seamless user experience. Industry analysts observe that this dual commitment to RISC-V by both a commercial giant and a grassroots community project indicates growing confidence in the architecture's viability for production environments. Although RISC-V chips currently lag behind in raw performance compared to established x86 and ARM processors, ongoing improvements in silicon design and fabrication suggest this gap will narrow. Support from major Linux distributions is pivotal to accelerating software ecosystem maturity, which has been a critical barrier to wider RISC-V adoption. Hardware manufacturers such as SiFive, Microchip, and Alibaba's semiconductor division are developing increasingly powerful RISC-V processors targeting servers and high-performance computing. Red Hat's engagement with these vendors is expected to facilitate optimisation efforts and certification programmes, ensuring that RHEL runs reliably on certified RISC-V platforms. This cooperation is vital as enterprises require not only compatibility but also assurances around security, stability, and long-term support when deploying new architectures. The initiative also ties into broader trends within the open-source community and the tech industry. Governments and large organisations are seeking to reduce dependency on single-source suppliers, especially in light of geopolitical tensions and supply chain vulnerabilities exposed in recent years. Open hardware initiatives like RISC-V are viewed as strategic assets that can drive innovation while enhancing security and sovereignty over critical technology infrastructure. ADVERTISEMENT Despite enthusiasm, challenges remain. Software ecosystem maturity is uneven; many applications and development tools require adaptation to fully leverage RISC-V capabilities. Furthermore, mainstream cloud providers have yet to offer widespread RISC-V hosting options, limiting deployment scenarios primarily to on-premises and experimental settings for now. However, companies such as Amazon Web Services have begun exploratory work with RISC-V instances, signalling potential expansion in the near term. Red Hat and Rocky Linux's pursuit of RISC-V support follows a pattern of early adoption seen in other Linux distributions such as Fedora, where RISC-V packages have been under development for some time. Their progress benefits from this groundwork, yet enterprise-grade readiness demands rigorous validation and comprehensive documentation to meet customer expectations. The growing adoption of RISC-V by major Linux providers may also stimulate innovation in adjacent fields. For example, edge computing deployments prioritising low power consumption and customised instruction sets stand to gain from enhanced RISC-V Linux support. Academic and research institutions involved in processor architecture development also benefit from improved access to stable operating systems, enabling faster prototyping and experimentation.
Business Wire
20-05-2025
- Business
- Business Wire
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
BOSTON--(BUSINESS WIRE)--SiFive, the gold standard for RISC-V, today announced a collaboration with Red Hat, the world's leading provider of enterprise open source solutions, to bring Red Hat Enterprise Linux support to the rapidly growing RISC-V community. Red Hat Enterprise Linux 10 is available in developer preview on the SiFive HiFive Premier TM P550 platform. This is an exciting expansion of the fast-growing global software ecosystem for RISC-V Share The SiFive HiFive Premier TM P550 provides a proven, high-performance RISC-V CPU development platform. Adding support for Red Hat Enterprise Linux 10, the latest version of the world's leading enterprise Linux platform, enables developers to create, optimize, and release new applications for the next generation of enterprise servers and cloud infrastructure on the RISC-V architecture. 'Empowering the software developer community is an important part of realizing our vision to enable our partners to deliver systems with a meaningfully lower total cost of ownership than incumbent platforms,' said Ian Ferguson, VP, Vertical Markets at SiFive. 'Delivering Red Hat Enterprise Linux 10 developer preview on the popular SiFive HiFive Premier P550 provides a strong foundation to inspire the next generation of enterprise workloads and AI applications optimized for RISC-V.' RISC-V provides enterprises and datacenter companies the flexibility needed to meet strict cost, power, and performance needs in the AI era. Both Red Hat and SiFive are active participants in the RISC-V Software Ecosystem (RISE) Project that is focused on optimizing open source software for deployment in RISC-V-based systems. SiFive's high performance RISC-V technology is already being used by large organizations to meet compute-intensive AI and machine learning workloads in the datacenter. 'The continued adoption of open source and open standard technologies continues to accelerate innovation across the industry,' said Ronald Pacheco, senior director, Red Hat Enterprise Linux Product and Ecosystem Strategy, Red Hat. 'With the growing demand for RISC-V, we are pleased to collaborate with SiFive to support Red Hat Enterprise Linux 10 deployments on SiFive HiFive Premier P550 to further empower developers with the power of the world's leading enterprise Linux platform wherever and however they choose to deploy.' The developer preview of Red Hat Enterprise Linux 10 is initially available for use on the SiFive HiFive Premier P550 platform. SiFive is collaborating with Red Hat to prepare Red Hat's product portfolio for future intersection with RISC-V server hardware from a diverse set of RISC-V suppliers. "Native Red Hat Enterprise Linux support on SiFive's HiFive Premier P550 board offers developers a substantial enterprise-grade toolchain for RISC-V. This is a pivotal step forward in enabling a full-stack ecosystem around open RISC-V hardware,' said Dave Altavilla, Principal Analyst – HotTech Vision and Analysis. To learn more about the SiFive HiFive Premier P550 development platform, please visit: About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's RISC-V compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. Red Hat, Red Hat Enterprise Linux, and the Red Hat logo, are trademarks or registered trademarks of Red Hat, Inc. or its subsidiaries in the U.S. and other countries. Linux® is the registered trademark of Linus Torvalds in the U.S. and other countries.
Associated Press
16-05-2025
- Automotive
- Associated Press
ECARX Debuts EXP01 Processor at RISC-V Summit Europe 2025, Outlines Next-Generation MCU Roadmap and Global RISC-V Strategy
SHANGHAI, May 16, 2025 (GLOBE NEWSWIRE) -- ECARX Holdings Inc. (Nasdaq: ECX) ('ECARX' or the 'Company'), a global mobility tech provider, announced the debut of its EXP01 processor built on the RISC-V architecture at the RISC-V Summit Europe 2025 which was held from May 12-15, 2025, in Paris. Alongside this technical breakthrough, ECARX also outlined its roadmap for the next-generation MCU, deepened technical collaborations with the RISC-V ecosystem, and reaffirmed its commitment to accelerating RISC-V adoption in intelligent mobility solutions. RISC-V is a completely open-source instruction-set architecture that provides a simple, modular foundation for building customized processors. Unlike proprietary chip designs, RISC-V lets engineers identify and select only the features they need, enabling faster innovation, lower power consumption, and optimized development costs across a broad range of auto electronic applications. ECARX showcased EXP01, its first processor design built on the 32-bit RISC-V ISA. EXP01 uses a dual-core safety architecture in which two identical cores run in unison to continuously verify each other's operation, earning it the highest level of functional safety certification, ISO 26262 ASIL-D. This fail-safe design delivers reliable performance for critical in-vehicle functions such as advanced driver assistance and intelligent cockpit interfaces, underscoring ECARX's robust capabilities in automotive-grade safety development and management. Building on this milestone, ECARX also outlined the R&D roadmap for its next-generation automotive-grade MCU, a scalable microcontroller specifically designed for intelligent cockpit and body-domain control applications. The MCU was developed to meet ISO 26262 ASIL-B safety standards and will support current and future encryption protocols, ensuring seamless compliance with international data regulations. During the event, ECARX's Head of R&D, Mr. Wei Jian, engaged in in-depth technical workshops with leading RISC-V developers, including StarFive Technology. These conversations are laying the groundwork for joint research and development initiatives to accelerate integration of RISC-V-based computing platforms into next-generation vehicle architectures worldwide. Mr. Ziyu Shen, Chairman, and CEO of ECARX, commented: 'EXP01 marks a critical step in our mission to deliver highly reliable open-architecture computing platforms for the automotive industry. Leveraging our global ecosystem of partnerships, we are continuously enhancing the performance and safety of our hardware and software stack, offering automakers a unique value proposition with several solutions that can be seamlessly customized for deployment in any market. RISC-V's open architecture drives faster innovation and optimizes costs, directly aligning with our goal to keep automakers at the forefront of technological change with cost-effective solutions. With our MCU roadmap and deepening collaborations, we are well positioned to lead the intelligent mobility revolution powered by RISC-V.' About ECARX ECARX (Nasdaq: ECX) is a global automotive technology provider with capabilities to deliver turnkey solutions for next-generation smart vehicles, from the system on a chip (SoC), to central computing platforms, and software. As automakers develop new electric vehicle architectures from the ground up, ECARX is developing full-stack solutions to enhance the user experience, while reducing complexity and cost. Founded in 2017 and listed on the Nasdaq in 2022, ECARX now has around 1,800 employees based in 12 major locations in China, UK, USA, Sweden and Germany. The co-founders are two automotive entrepreneurs, Chairman and CEO Ziyu Shen, and Eric Li (Li Shufu), who is also the founder and chairman of Zhejiang Geely Holding Group — with ownership interests in global brands including Lotus, Lynk & Co, Geely Galaxy, Polestar, smart, and Volvo Cars. ECARX also works with other well-known automakers, including Volkswagen Group, FAW Group and Dongfeng Peugeot-Citroën. To date, ECARX products can be found in over 8.7 million vehicles worldwide. Forward-Looking Statements This release contains statements that are forward-looking statements within the meaning of the U.S. Private Securities Litigation Reform Act of 1995. These statements are based on management's beliefs and expectations as well as on assumptions made by and data currently available to management, appear in a number of places throughout this document and include statements regarding, amongst other things, results of operations, financial condition, liquidity, prospects, growth, strategies and the industry in which we operate. The use of words 'expects', 'intends', 'anticipates', 'estimates', 'predicts', 'believes', 'should', 'potential', 'may', 'preliminary', 'forecast', 'objective', 'plan', or 'target', and other similar expressions are intended to identify forward-looking statements. These forward-looking statements are not guarantees of future performance and are subject to a number of risks and uncertainties that could cause actual results to differ materially, including, but not limited to, statements regarding our intentions, beliefs or current expectations concerning, among other things, results of operations, financial condition, liquidity, prospects, growth, strategies, future market conditions or economic performance and developments in the capital and credit markets and expected future financial performance, and the markets in which we operate. For a discussion of these and other risks and uncertainties that could cause actual results to differ materially from those expressed in any forward-looking statement, see ECARX's filings with the U.S. Securities and Exchange Commission. ECARX undertakes no obligation to update or revise forward-looking statements to reflect subsequent events or circumstances, except as required by applicable law. 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