Latest news with #RISC-VInternational
Forbes
5 days ago
- Business
- Forbes
RISC-V's Ascent Could Reshape The Global Compute Landscape
Frans Sijstermans of Nvidia On Stage At RISC-V Summit Announcing CUDA Support For RISC-V Host ... More Processors For decades, chip architectures have been dominated by a pair of towering incumbents—x86 and Arm—defining and powering everything from laptops to hyperscale data centers. But in recent years, the open-standard RISC-V instruction set architecture has evolved from an academic project into a legitimate disruptor, increasingly embedded across a diverse range of compute platforms. Today, amid a wave of industry consolidation, geopolitical shifts, and an AI-driven workload explosion, RISC-V is accelerating toward mainstream relevance with some of the largest chip players backing it. RISC-V: From Academic Roots To A Billion Cores Milestone RISC-V was born in 2010 at UC Berkeley, designed as a clean-slate, royalty-free ISA optimized for modern workloads and extensibility. Its founding team—still active in steering the standard through RISC-V International (RVI)—envisioned an open hardware ecosystem that encouraged innovation across both academia and industry. That vision has been bearing fruit in recent years and in fact, in 2024, Nvidia shipp Nvidia's GeForce RTX 5090 Graphics Card Utilizes RISC-V Cores For Its AMP AI Workload Scheduler ed over one billion RISC-V cores onboard its GPUs. These cores serve as microcontrollers and security processors, managing tasks like power, telemetry, and safety-critical logic, where lightweight, highly customizable architectures excel. However, this was just one of many proof points in validation of the technology. And just a few days ago, Nvidia announced CUDA support on RISC-V host system processors was coming, which would enable developers to write GPU-accelerated applications for RISC-V CPUs. This is very big news, as it now also positions RISC-V as a viable general purpose compute platform, capable of driving heterogeneous AI workloads, particularly in embedded, edge, and autonomous systems where Arm once reigned supreme. For a company as dominant in accelerated computing as Nvidia to validate RISC-V as a CUDA host is a sea change, and a green light to broader ecosystem adoption. Obviously, Nvidia sees that the future of RISC-V processor hosts in clients and the data center is already taking shape. Few companies have done more to commercialize RISC-V solutions than SiFive. Founded by three of the ISA's creators, SiFive has emerged as a flagship IP vendor in the space, delivering RISC-V processor cores from ultra-efficient MCUs to high-performance vector and application-class CPUs. Its IP is already found in products from major cloud and AI companies, and SiFive continues to expand its footprint. A recent partnership with Synopsys helps streamline system-on-chip designs using familiar EDA tools, while support from Red Hat and Canonical ensures full Linux compatibility out of the box. With respect to other large players, Google is also reportedly using SiFive cores in upcoming TPU designs, further cementing its status as a go-to RISC-V partner. Internally, SiFive has expanded its focus to defense and aerospace, while also targeting automotive and edge AI, segments where vector performance for heavy compute and image processing, deterministic execution, and ISA flexibility are mission critical. A strong ISA needs a strong ecosystem, and RISC-V is seeing meaningful support across all levels of the stack. Android is being ported to RISC-V, with full RVA23 compliance under development. Ubuntu and Red Hat Enterprise Linux are already available on SiFive hardware, giving software developers familiar toolchains. Tenstorrent, a new AI chip start-up co-founded by legendary chip architect Jim Keller, and also a SiFive customer, is designing RISC-V-based CPUs targeting AI and high-performance edge workloads. Meanwhile, Ahead Computing, another RISC-V start-up with ties to Intel talent, is quietly making strides in server-class designs. Finally, all of the "Magnificent Seven" tech giants reportedly use RISC-V in some capacity, with five of them working directly with SiFive (and likely others). These include datacenter service processors, AI accelerators, and custom embedded cores—proof that RISC-V's flexibility fits many application use cases. What makes RISC-V different isn't just the open license, it's the ability to tailor the architecture to the application. Unlike x86 or Arm, which impose fixed instruction sets and licensing constraints, RISC-V lets chipmakers design exactly what they need, nothing more, nothing less. That's a major win in the AI era, where model diversity and workload complexity demand hardware tuned for domain specific workloads and energy efficiency. That said, it's also critical geopolitically. With nations racing to secure their own chip supply chains, RISC-V has become a strategic enabler of semiconductor sovereignty. In the US, DoD-aligned programs are increasingly turning to open ISAs to avoid reliance on foreign-controlled IP. Even GlobalFoundries' acquisition of MIPS plays into the RISC-V narrative, expanding IP offerings while avoiding competitive overlap. Of course, despite its momentum, RISC-V still faces headwinds. The software stack, though rapidly improving, lacks the decades of legacy optimization behind x86 or Arm architectures. Toolchain fragmentation, limited driver support, and early-stage debugging tools still pose barriers, particularly in high-performance compute. Governance is another concern. While RISC-V International continues to standardize extensions and promote compatibility, the risk of fragmentation remains if vendors diverge too far from the core spec. Yet even with those challenges, the architectural advantages are strong. In a market shifting toward domain-specific compute, chiplet-based design, and heterogeneous acceleration, RISC-V offers a level of flexibility, openness, and modularity that few others can match. Obviously, RISC-V won't topple Arm or x86 overnight, but that's not the point. Instead, it's now beginning to establish beachheads in markets where customization, efficiency, and freedom from licensing constraints are competitive advantages. As Nvidia, Google, Red Hat, and others embrace RISC-V not just for microcontrollers but for host processors, AI pipelines, and full-stack development, the architecture is maturing from just an alternative to a strategic asset. In today's silicon landscape that's so often dominated by constrained IP entanglements, RISC-V is offering a different path—one that's open, adaptable, and increasingly hard to ignore.
South China Morning Post
22-07-2025
- Business
- South China Morning Post
Nvidia to support RISC-V processors in latest boost to China's chip self-sufficiency drive
Nvidia said it was working to support the RISC-V chip architecture on its CUDA software platform, a move expected to boost the open-source movement that China is betting on as part of its tech self-sufficiency drive. 'We are porting CUDA to the RISC-V architecture,' Frans Sijsterman, vice-president of hardware engineering at Nvidia, said at the 2025 RISC-V Summit in Shanghai last week. RISC-V central processing units (CPUs) could then be used as the main application processor in Nvidia systems, Sijsterman said, although he did not give a timeline for the plan. RISC-V, the fifth generation of the open-sourced Reduced Instruction Set Computer architecture for CPUs, is free for anyone to use and modify. First developed in 2010 by researchers at the University of California, Berkeley, RISC-V is now managed by RISC-V International, a Zurich-based non-profit organisation. The move represents a major step by Nvidia to boost the development of the open-source chip architecture in AI computing. CUDA previously only supported two mainstream chip platforms: x86, a complex instruction set that dominates personal computers, and the eponymous architecture of British firm Arm Holdings , which is widely used in the smartphone sector.
Yahoo
20-02-2025
- Business
- Yahoo
Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
Active Participant in RISC-V academic projects worldwide and the RISC-V International Certification Steering Committee SAN JOSE, Calif., Feb. 20, 2025 (GLOBE NEWSWIRE) -- Breker Verification Systems today confirmed its RISC-V SystemVIP library components and test suite synthesis product portfolio is deployed in more than 15 commercial RISC-V semiconductor design projects, while its RISC-V products are used in several large-scale academic projects. Large, complex application processor projects that range from data center, automotive and AI accelerator to consumer device applications rely on Breker's RISC-V CoreAssurance™, SoCReady™ and Cache Coherency SystemVIPs across the RISC-V core and SoC verification stack. Breker executives are heading working groups in the evolving RISC-V International certification program. 'Breker Verification Systems' products provide significant advantages on top of standard verification solutions, especially for the most challenging verification problems,' affirms Ty Garibay, President of Condor Computing. 'Applying these approaches to RISC-V processor design was a natural extension, and leveraging this technology in the development of our high-performance CPU IP is already paying dividends.' Breker's test suite synthesis solution and SystemVIP library allow for enhanced verification coverage while significantly reducing test development time for complex scenarios. The verification of processor cores that leverage the RISC-V Open Instruction Set Architecture (ISA) requires testing specialized, unique scenarios. Breker's RISC-V synthesized SystemVIPs make use of AI Planning Algorithms, cross-test multiplication and concurrent, multi-threaded scheduling provide rigorous testing from randomized instructions to unique coherency, paging and other complex system integration validation. 'MIPS RISC-V cores represent the state-of-the-art in advanced application processor solutions,' notes Steve Mullinnix, Senior Director, Design Verification, MIPS. 'Working with Breker, we are able to verify complex, compounded scenarios unique to these devices quickly and efficiently.' Breker is cooperating with academic institutions including Harvey Mudd College in Claremont, Calif., and Oklahoma University, developers of the Wally open-source processor core, and ETH Zurich in Zurich, Switzerland, that produced the Ariane processor core. Breker has provided application-level tests for these institutions while collaborating on next-generation verification environments. 'Breker is at the forefront of RISC-V verification,' comments David Harris, the Harvey S. Mudd Professor of Engineering Design. 'It's first-rate SystemVIP synthesis platform is a breakthrough verification tool and an effective problem-solver for our RISC-V programs.' Additionally, executives from Breker are leading two working groups within RISC-V International's Certification Steering Committee to develop a program to provide a quality stamp based on extensive, independent architectural testing. 'The rate of adoption of our tools is remarkable and supports our belief that test suite synthesis is a must have tool for every RISC-V design project,' says David Kelf, Breker's Chief Executive Officer. 'Our efforts to build more features will continue as will our willingness to partner with leading project groups and industry organizations helping to cement the RISC-V ISA place across the semiconductor industry.' Breker's RISC-V CoreAssurance, SoCReady and SystemVIPBreker unveiled RISC-V CoreAssurance, SoCReady and SystemVIP in June 2024, along with a complete range of tests for the entire RISC-V core verification stack. Starting with randomized instruction generation and microarchitectural scenarios, SystemVIP includes unique tests that check all integrity levels ensuring the smooth application of the core into an SoC, regardless of architecture, and the evaluation of possible performance and power bottlenecks and functional issues. The SystemVIP can be extended for custom RISC-V instructions to be fully incorporated into the complete test suite crossed with other tests. It is self-checking and incorporates debug and coverage analysis solutions and can be ported across simulation, emulation, prototyping, post-silicon and virtual platform environments. Breker's SystemVIP is used for a variety of complex RISC-V core designs, including system coherency in a multicore SoC integrity test sets, high-coverage core test, power domain switching, hardware security access rules and automated packet generation Breker at DVCon U.S. February 24-27 in San JoseBreker will exhibit and demonstrate its RISC-V CoreAssurance and SoCReady SystemVIP and Trek Test Suite Synthesis solutions at DVCon U.S. February 24-26 at the DoubleTree Hotel in San Jose, Calif. It will present a workshop titled 'Complex Verification Example: RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC platforms' Monday, February 24, from 3:30 p.m. until 5 p.m. in the Oak Room. To arrange a demonstration or private meeting, send email to info@ About Breker Verification SystemsBreker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker solutions easily layer into existing environments and operate across simulation, emulation and prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Altera (now Intel), Analog Devices, Broadcom, IBM and other companies leveraging Breker's solutions are available on the Breker website. Engage with Breker at:Website: @BrekerSystemsLinkedIn: TrekSoC, TrekSoC-Si, TrekBox and SoC Scenario Modeling are registered trademark of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products. For more information, contact:Nanette CollinsPublic Relations for Breker Verification Systemsnanette@ in to access your portfolio
