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Business Upturn
5 hours ago
- Business
- Business Upturn
VeriSilicon Expands DSP Portfolio with Silicon-Proven ZSP5000 Vision Core Seriesfor Edge Intelligence
By Business Wire India Published on June 26, 2025, 09:36 IST Shanghai, China: VeriSilicon ( today released the ZSP5000 Digital Signal Processing (DSP) series IPs, which are based on its fifth-generation silicon-proven DSP architecture. This product line adopts a highly scalable and energy-efficient design, and has been deeply optimized for compute-intensive workloads such as computer vision and embedded AI. Combined with the configurable nature of the architecture, this series of IP can provide excellent solutions with both energy and computing efficiency for various edge devices. The ZSP5000 series IPs include ZSP5000, ZSP5000UL, ZSP5000L, and ZSP5000H, delivering scalable vector processing performance ranging from 32 to 256 8-bit Multiply-Accumulate (MAC) operations per cycle. For even higher performance, VeriSilicon's multi-core ZSP5400H can combine multiple ZSP5000H cores in a multi-cluster architecture to further scale computing capability. The ZSP5000 series features a rich and intuitive instruction set optimized for ease of programming and efficient performance tuning, while its dedicated instructions accelerate common imaging and signal processing tasks such as vector-scalar arithmetic, horizontal reductions, permutations, shifts, table lookups, clamping, and averaging. It integrates the ZTurbo coprocessor interface, allowing customers to easily add custom instructions and hardware accelerators within the same pipeline, and is compatible with the OpenCV Application Programming Interface (API), ensuring seamless integration with the mainstream computer vision frameworks. Additionally, the ZSP5000 series is equipped with a full-featured memory subsystem, a multi-channel 3D DMA engine, and a scalable multicore configuration, supporting flexible deployment for a broad spectrum of applications. The ZSP5000 series IPs are backward compatible with VeriSilicon's scalar ZSPNano series, efficiently handling mixed MCU and DSP workloads. VeriSilicon also offers comprehensive ZView development tools, including an Eclipse-based Integrated Development Environment (IDE), cycle-accurate simulator, optimizing compiler, debugger, and profiling tools, streamlining software development and system integration. 'With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series. It supports the industry-standard OpenCV API, enables streamlined interfacing with NPUs via our FLEXA interface, and integrates built-in audio processing capabilities for multi-modal applications,' said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. 'Energy efficiency is key at the edge, and the ZSP5000 series IPs feature an optimized memory access architecture to minimize processor power consumption. It also features ZTurbo, a custom instruction extension mechanism designed for targeted applications, which enables further power and performance optimization through seamless integration of hardware accelerators. Our leading customers are already leveraging these capabilities to achieve significant advancements in power and performance.' About VeriSilicon VeriSilicon is committed to providing customers with platform-based, all-around, one-stop custom silicon services and semiconductor IP licensing services leveraging its in-house semiconductor IP. For more information, please visit: View source version on Disclaimer: The above press release comes to you under an arrangement with Business Wire. Business Upturn takes no editorial responsibility for the same. Ahmedabad Plane Crash Business Wire India, established in 2002, India's premier media distribution company ensures guaranteed media coverage through its network of 30+ cities and top news agencies.
Business Wire
12 hours ago
- Business
- Business Wire
VeriSilicon Expands DSP Portfolio with Silicon-Proven ZSP5000 Vision Core Series for Edge Intelligence
SHANGHAI--(BUSINESS WIRE)--VeriSilicon ( today released the ZSP5000 Digital Signal Processing (DSP) series IPs, which are based on its fifth-generation silicon-proven DSP architecture. This product line adopts a highly scalable and energy-efficient design, and has been deeply optimized for compute-intensive workloads such as computer vision and embedded AI. Combined with the configurable nature of the architecture, this series of IP can provide excellent solutions with both energy and computing efficiency for various edge devices. With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series. Share The ZSP5000 series IPs include ZSP5000, ZSP5000UL, ZSP5000L, and ZSP5000H, delivering scalable vector processing performance ranging from 32 to 256 8-bit Multiply-Accumulate (MAC) operations per cycle. For even higher performance, VeriSilicon's multi-core ZSP5400H can combine multiple ZSP5000H cores in a multi-cluster architecture to further scale computing capability. The ZSP5000 series features a rich and intuitive instruction set optimized for ease of programming and efficient performance tuning, while its dedicated instructions accelerate common imaging and signal processing tasks such as vector-scalar arithmetic, horizontal reductions, permutations, shifts, table lookups, clamping, and averaging. It integrates the ZTurbo coprocessor interface, allowing customers to easily add custom instructions and hardware accelerators within the same pipeline, and is compatible with the OpenCV Application Programming Interface (API), ensuring seamless integration with the mainstream computer vision frameworks. Additionally, the ZSP5000 series is equipped with a full-featured memory subsystem, a multi-channel 3D DMA engine, and a scalable multicore configuration, supporting flexible deployment for a broad spectrum of applications. The ZSP5000 series IPs are backward compatible with VeriSilicon's scalar ZSPNano series, efficiently handling mixed MCU and DSP workloads. VeriSilicon also offers comprehensive ZView development tools, including an Eclipse-based Integrated Development Environment (IDE), cycle-accurate simulator, optimizing compiler, debugger, and profiling tools, streamlining software development and system integration. 'With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series. It supports the industry-standard OpenCV API, enables streamlined interfacing with NPUs via our FLEXA interface, and integrates built-in audio processing capabilities for multi-modal applications,' said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. 'Energy efficiency is key at the edge, and the ZSP5000 series IPs feature an optimized memory access architecture to minimize processor power consumption. It also features ZTurbo, a custom instruction extension mechanism designed for targeted applications, which enables further power and performance optimization through seamless integration of hardware accelerators. Our leading customers are already leveraging these capabilities to achieve significant advancements in power and performance.' VeriSilicon is committed to providing customers with platform-based, all-around, one-stop custom silicon services and semiconductor IP licensing services leveraging its in-house semiconductor IP. For more information, please visit:
Business Wire
09-06-2025
- Business
- Business Wire
VeriSilicon's Ultra-Low Energy NPU Provides Over 40 TOPS for On-Device LLM Inference in Mobile Applications
SHANGHAI--(BUSINESS WIRE)--VeriSilicon ( today announced that its ultra-low energy and high-performance Neural Network Processing Unit (NPU) IP now supports on-device inference of large language models (LLMs) with AI computing performance scaling beyond 40 TOPS. This energy-efficient NPU architecture is specifically designed to meet the increasing demand for generative AI capabilities on mobile platforms. It not only delivers powerful computing performance for AI PCs and other end devices, but is also optimized to meet the increasingly stringent energy efficiency challenges of AI phones and other mobile platforms. Built on a highly configurable and scalable architecture, VeriSilicon's ultra-low power NPU IP supports mixed-precision computation, advanced sparsity optimization, and parallel processing. Built on a highly configurable and scalable architecture, VeriSilicon's ultra-low energy NPU IP supports mixed-precision computation, advanced sparsity optimization, and parallel processing. Its design incorporates efficient memory management and sparsity-aware acceleration, which reduce computational overhead and latency, ensuring smooth and responsive AI processing. It supports hundreds of AI algorithms including AI-NR and AI-SR, and leading AI models such as Stable Diffusion and LLaMA-7B. Moreover, it can be seamlessly integrated with VeriSilicon's other processing IPs to enable heterogeneous computing, empowering SoC designers to develop comprehensive AI solutions that meet diverse application needs. VeriSilicon's ultra-low energy NPU IP also supports popular AI frameworks such as TensorFlow Lite, ONNX, and PyTorch, thereby accelerating deployment and simplifying integration for customers across various AI use cases. 'Mobile devices, such as smartphones, are evolving into personal AI servers. With the rapid advancement of AIGC and multi-modal LLM technologies, the demand for AI computing is growing exponentially and becoming a key differentiator in mobile products,' said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. 'One of the most critical challenges in supporting such high AI computing workloads is energy consumption control. VeriSilicon has been continuously investing in ultra-low energy NPU development for AI phones and AI PCs. Through close collaboration with leading SoC partners, we are excited to see that our technology has been realized in silicon for next-generation AI phones and AI PCs.' About VeriSilicon
Business Wire
09-06-2025
- Business
- Business Wire
VeriSilicon's Scalable High-Performance GPGPU-AI Computing IPs Empower Automotive and Edge Server AI Solutions
SHANGHAI--(BUSINESS WIRE)--VeriSilicon ( today announced the latest advancements in its high-performance and scalable GPGPU-AI computing IPs, which are now empowering next-generation automotive electronics and edge server applications. Combining programmable parallel computing with a dedicated Artificial Intelligence (AI) accelerator, these IPs offer exceptional computing density for demanding AI workloads such as Large Language Model (LLM) inference, multimodal perception, and real-time decision-making in thermally and power-constrained environments. VeriSilicon's GPGPU-AI computing processors are architected to tightly integrate GPGPU computing with AI accelerator at fine-grained levels. VeriSilicon's GPGPU-AI computing IPs are based on a high-performance General Purpose Graphics Processing Unit (GPGPU) architecture with an integrated dedicated AI accelerator, delivering outstanding computing capabilities to AI applications. The programmable AI accelerator and sparsity-aware computing engine accelerate transformer-based and matrix-intensive models through advanced scheduling techniques. These IPs also support a broad range of data formats for mixed-precision computing, including INT4/8, FP4/8, BF16, FP16/32/64, and TF32, and are designed with high-bandwidth interfaces of 3D-stacked memory, LPDDR5X, HBM, as well as PCIe Gen5/Gen6 and CXL. They are also capable of multi-chip and multi-card scale-out expansion, offering system-level scalability for large-scale AI application deployments. VeriSilicon's GPGPU-AI computing IPs provide native support for popular AI frameworks for both training and inference, such as PyTorch, TensorFlow, ONNX, and TVM. These IPs also support General Purpose Computing Language (GPCL) which is compatible with mainstream GPGPU programming languages, and widely used compilers. These capabilities are well aligned with the computing and scalability requirements of today's leading LLMs, including models such as DeepSeek. 'The demand for AI computing on edge servers, both for inference and incremental training, is growing exponentially. This surge requires not only high efficiency but also strong programmability. VeriSilicon's GPGPU-AI computing processors are architected to tightly integrate GPGPU computing with AI accelerator at fine-grained levels. The advantages of this architecture have already been validated in multiple high-performance AI computing systems,' said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. 'The recent breakthroughs from DeepSeek further amplify the need for maximized AI computing efficiency to address increasingly demanding workloads. Our latest GPGPU-AI computing IPs have been enhanced to efficiently support Mixture-of-Experts (MoE) models and optimize inter-core communication. Through close collaboration with multiple leading AI computing customers, we have extended our architecture to fully leverage the abundant bandwidth offered by 3D-stacked memory technologies. VeriSilicon continues to work hand-in-hand with ecosystem partners to drive real-world mass adoption of these advanced capabilities.' VeriSilicon is committed to providing customers with platform-based, all-around, one-stop custom silicon services and semiconductor IP licensing services leveraging its in-house semiconductor IP. For more information, please visit:
Yahoo
16-04-2025
- Business
- Yahoo
VeriSilicon Launches Ultra-Low Power OpenGL ES GPU with Hybrid 3D/2.5D Rendering for Wearables
GCNano3DVG GPU IP introduces content-aware rendering to maximize efficiency in wearable applications SHANGHAI, April 16, 2025--(BUSINESS WIRE)--VeriSilicon ( today announced the launch of GCNano3DVG, a new ultra-low power graphics processing unit (GPU) IP designed specifically for wearable and other compact, battery-powered devices requiring dynamic graphics rendering. Featuring both 3D and 2.5D graphics rendering capabilities, GCNano3DVG delivers an optimal balance between visual performance and power efficiency, making it ideal for a wide range of applications including smartwatches, smart bracelets, and AI/AR glasses. VeriSilicon's GCNano3DVG IP combines optimized hardware pipelines with a lightweight and configurable software stack to deliver efficient, low-power graphics processing. It features separate rendering pipelines for 3D and 2.5D graphics, accelerating the rendering of complex scenes composed of 3D objects and vector graphics. These pipelines are fine-tuned for improved performance, power, and area (PPA). Additionally, the unified command engine and multiple CPU-GPU synchronization mechanisms further reduce system overhead, while DDR-less configurations utilizing Static Random-Access Memory (SRAM) or Pseudo-Static Random-Access Memory (PSRAM) offer a cost-effective and low-power solution for embedded graphics processing. GCNano3DVG supports VeriSilicon's GLLite and VGLite Application Programming Interfaces (APIs) for 3D and 2.5D/2D graphics rendering. The GLLite driver is highly configurable, providing full OpenGL ES 2.0 compliance with an optional runtime OpenGL Shading Language (GLSL) shader compiler, or operating in OpenGL ES 1.1 fixed-function pipeline mode for minimal memory usage. It also supports rendering of Khronos' Graphics Library Transmission Format (glTF), enabling efficient handling of 3D assets for modern applications. The VGLite driver is compatible with popular vector graphics libraries such as LVGL and NanoVG. GLLite and VGLite APIs can be used flexibly and synchronously within a single application, providing versatile and high-performance graphics solutions across diverse embedded use cases. "As wearable applications continue to expand, the demand for more immersive user interfaces featuring 3D-rendered content is growing, while ultra-low power consumption is still expected," said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. "To address these demands, we designed a hybrid GPU architecture built upon our ultra-low power Nano 3D and Nano 2.5D GPU technologies. This innovation enables efficient rendering of mixed 3D and 2.5D content with minimal power consumption." VeriSilicon's GCNano3DVG GPU IP is now available for licensing. For more information or collaboration inquiries, please visit About VeriSilicon VeriSilicon is committed to providing customers with platform-based, all-around, one-stop custom silicon services and semiconductor IP licensing services leveraging its in-house semiconductor IP. For more information, please visit: View source version on Contacts Media Contact: press@ Sign in to access your portfolio
