SK hynix Presents Future DRAM Technology Roadmap at IEEE VLSI 2025
- Considering switching to 4F² VG platform from 10-nm level technology due to scaling limitation with current DRAM technology
- Company to present long-term technological vision and work with industry to bring future of DRAM into reality
SEOUL, South Korea, June 9, 2025 /PRNewswire/ -- SK hynix Inc. (or "the company", www.skhynix.com) announced today that it presented a new DRAM technology roadmap for the next 30 years and the direction for a sustainable innovation at the IEEE VLSI symposium 2025* held in Kyoto, Japan.
* IEEE VLSI (Institute of Electrical and Electronics Engineers Very Large Scale Integration) symposium: One of the most prestigious academic events in the field of semiconductor circuit and process technology, presenting academic achievement in next-generation semiconductor, AI, memory chip and packaging. The symposium is held in turn in United States and Japan annually.
Cha Seon Yong, Chief Technology Officer (CTO) of SK hynix, delivered on June 10th a plenary session on "Driving Innovation in DRAM Technology: Towards a Sustainable Future".
In his speech, CTO Cha explained that it is increasingly difficult to improve performance and capacity with scaling through current technology platform*. "In order to overcome such limitations, SK hynix will apply the 4F² VG (Vertical Gate) platform and 3D DRAM technology to technologies of 10-nanometer level or below with innovation in structure, material and components," he said.
* Tech Platform: A technological framework that can be applied to various generations of products
The 4F²* VG** platform is a next-generation memory technology that minimizes the cell area of DRAM and enables high-integration, high-speed and low-power through a vertical gate structure.
* 4F²: The area occupied by one cell, a unit to store data, is indicated as F2. F indicates the minimum feature size of a semiconductor. Therefore, 4F2 is an integration technology to put more cells in a chip which one cell occupies an area of 2F by 2F.
** VG (Vertical Gate): A structure that a gate, which acts as a switch of a transistor, is vertically placed and surrounded by channels. Currently, it is a flat structure where a gate is laid horizontally on top of channels.
Currently, 6F2 cells are common, but by applying 4F2 cell and wafer bonding technology that puts the circuit part below the cell area, cell efficiency and electrical characteristics can be improved.
CTO Cha also introduced 3D DRAM as the main pillar for the future DRAM along with VG. CTO Cha said that although some in the industry warn of cost increase according to the number of layers stacked, it can be solved by constant technological innovation.
Along with structural breakthrough, the company will also strive to find a new growth engine by sophisticating technologies of critical materials and components of DRAM to lay foundation for the next 30 years.
"Until around 2010, DRAM technology was expected to face limitations at 20 nanometers, but with constant innovation, we have made it this far," said CTO Cha. "SK hynix will continue to guide the future of long-term technological innovation to be a milestone for young engineers in the field of DRAM and maintain cooperation within the industry to bring future of DRAM into reality."
On the last day of the event, Joodong Park, vice president who leads the Next Gen DRAM TF, will present his findings from a recent research on how VG and wafer bonding technology affect the electrical characteristics of DRAM.
About SK hynix Inc.
SK hynix Inc., headquartered in Korea, is the world's top tier semiconductor supplier offering Dynamic Random Access Memory chips ("DRAM") and flash memory chips ("NAND flash") for a wide range of distinguished customers globally. The Company's shares are traded on the Korea Exchange, and the Global Depository shares are listed on the Luxembourg Stock Exchange. Further information about SK hynix is available at www.skhynix.com, news.skhynix.com.
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SOURCE SK hynix Inc.
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