Intel's Lunar Lake intricacies revealed in new high-resolution die shots

Yahoo

18-05-2025

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Lunar Lake unequivocally shook the market by blending an ultra-efficient design typically seen in Arm-based SoCs with the established foundation of x86. Fritzchens Fritz, a renowned hardware enthusiast known for capturing incredibly detailed and high-resolution die shots of CPUs, dissected a Lunar Lake sample, offering us a look at its internals and Intel's meticulous engineering.
Developing Lunar Lake required Intel to walk a strategic tightrope between cost and a good product. The result is extremely similar to that of Arm-based alternatives from Qualcomm while efficiently trading blows with Apple Silicon. Innovation isn't free, however, as Lunar Lake-powered laptops still hover in the four-figure territory. Even ex-CEO Pat Gelsinger characterized Lunar Lake as "a one-off" design, which explains why Intel's leaked roadmaps do not mention a successor.
Despite sharing the same core microarchitectures and process node as Arrow Lake, Intel took a completely different development approach with Lunar Lake. The TSMC N3B fabbed Compute Tile hosts four Lion Cove-based Performance (P) cores, sharing 12MB of L3 cache, with 2.5MB of private L2 cache per P-core. As opposed to Arrow Lake, the Skymont-based efficiency core cluster (E) doesn't share the same L3 cache pool, but sits on a "Low Power Island" with its own dedicated L2 cache (4MB). Next to E-cores is the NPU (Neural Processing Unit), which is believed to have six NCE (Neural Compute Engines) for almost 48 TOPS of AI performance.
The Compute Tile is also home to a Battlemage-based integrated GPU with up to eight Xe2-LPG cores and the Media Engine. Intel has essentially packed all key processing elements on one chiplet, significantly reducing inter-die communication's latency and power consumption. Intel also includes an 8MB System-Level-Cache (SLC) cache next to the memory controller, similar to Arm SoCs, which is shared between CPU cores, the integrated GPU, the NPU, and Media Engines. To further tighten integration and reduce latency, the memory physical layer is located directly on top of the Compute Tile, just below the two on-package, soldered, and non-upgradeable LPDDR5x-8533 ICs (16GB or 32GB) that function as the SoC's main memory.
Beneath the Compute Tile is the Platform Controller Tile based on TSMC's N6 process and a dummy tile for structural rigidity. The Platform Controller Tile can be considered the I/O Extender Tile with Arrow Lake, even though Intel internally referred to it as Lunar Lake's SoC Tile, based on leaks. This chiplet packs key HSIO and LSIO components, such as USB, Thunderbolt, and PCIe 4.0/5.0 interfaces, as well as Bluetooth and Wi-FI connectivity. All these chiplets are hosted atop a 22FFL-based active interposer, connected via Intel's Foveros 3D packaging technology.
These are just the chip's overall specifications; the precise arrangement varies, as it's impossible to know how Intel has laid out all these components without help from an engineer. All annotations are guesses based on visual cues, and each analyst may offer different interpretations.
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