Latest news with #RibbonFET
Forbes
29-04-2025
- Business
- Forbes
Intel Foundry And Synopsys Collaborate To Fast-Track 18A Chip Development
Intel CEO Lip-Bu Tan On Stage At Intel Foundry Direct Connect With Synopsys President And CEO ... More Sassine Ghazi In a joint announcement reflecting the growing importance of ecosystem collaboration in semiconductor design, Synopsys and Intel Foundry have expanded their partnership in support of chip development on Intel's 18A and 18A-P process technologies. This engagement aims to streamline and scale next-generation chip design for applications in AI, HPC, data center, client PC and mobile platforms. As Intel continues to evolve its foundry strategy under the leadership of its new CEO Lip-Bu Tan, collaborations with EDA and core IP providers like Synopsys are key to enabling a competitive and accessible design infrastructure for customers targeting Intel's new advanced process nodes. At the center of the announcement is Intel's 18A chip process, which introduces RibbonFET (Intel's gate-all-around transistor design) and PowerVia (backside power delivery), among other cutting-edge semiconductor design technologies. These innovations are key enablers that improve both performance and power efficiency of chips built on Intel processes at scale. Intel's 18A-P variant builds on this by offering additional optimization for performance-critical applications, and with better transistor density as well. Synopsys Electronic Design Automation Tools And IP Solutions To Accelerate Chip Design On Intel 18A To help design teams adopt these nodes effectively, Synopsys has certified its digital and analog EDA flows for Intel 18A, and those flows are now production-ready for 18A-P. Synopsys also provides a broad library of silicon-proven IP, including chip and system interfaces and foundation IP essential for building advanced system-on-chip designs. The availability of validated tools and IP is critical for customers seeking to reduce development timelines and manage risk when targeting these advanced chip fab nodes. In addition to process design support, the partnership also includes an optimized EDA reference flow for Intel's EMIB-T (Embedded Multi-die Interconnect Bridge Technology), a 2.5D advanced chip packaging solution that facilitates high-bandwidth integration across multiple dies within a single package. The reference flow supports a unified exploration-to-signoff platform, allowing design teams to manage 2.5D and 3D multi-die architectures more efficiently. This is particularly relevant as chip and system-level integration increasingly supplements traditional semiconductor node scaling (Moore's Law) in driving performance and functionality. Intel EMIB-T 2.5D Packaging Technology For Multi-Die System On Chip Designs EMIB-T and related advanced chip packaging technologies are an Intel strong suit for next-generation designs, particularly in data center AI applications, where compute density with better memory proximity helps drive performance. A certified EDA flow can reduce the complexity associated with these packaging technologies and support greater adoption across the industry. Looking ahead, Synopsys and Intel Foundry are also working together on early design enablement for Intel's 14A-E node, which is currently in development. While technical details are still scarce, 14A-E is expected to extend the architectural and manufacturing improvements introduced with 18A with 15 to 20% better performance-per-watt characteristics. By engaging early in the development of tools, flows and IP for 14A-E, the two companies aim to ensure that design infrastructure is in place when the process becomes commercially available, currently slated for late 2026 into early 2027. This approach reflects a broader trend toward concurrent design tool process co-optimization as process chip manufacturing nodes become more complex. This collaboration is aligned with Intel Foundry's broader strategy to build a complete ecosystem of tools, IP, and packaging capabilities that lower the barrier for entry for fabless semiconductor companies, like NVIDIA, Qualcomm, AMD, Broadcom, hot chip and tech start-ups, and many others. Having production-ready flows and validated IP in place is essential for serving both internal product groups at Intel and external customers. For Synopsys, the partnership reinforces its leadership in EDA enablement at advanced nodes and its commitment to supporting emerging packaging and system-level design methodologies. As complexity rises across the design stack, the need for integrated, validated solutions will continue to grow. From a market perspective, the announcement reflects how ecosystem partnerships are becoming foundational to delivering innovation at the angstrom scale. By working in parallel across process development, packaging and design flows, Intel and Synopsys customers can mitigate risk and shorten development cycles. The expanded collaboration between Synopsys and Intel Foundry provides a structured path for design teams targeting Intel's advanced process technologies, including 18A, 18A-P, and the future 14A-E node. With certified EDA flows, a broad IP portfolio, and advanced packaging support for EMIB-T, the partnership addresses key challenges in modern chip development. It will be interesting to track how the two companies progress as new external customers adopt Intel's 18A and advanced process nodes for state-side manufacturing here in the US.
Yahoo
29-04-2025
- Business
- Yahoo
Intel's Next Chip Node, 14A, to Boost CPU Speeds With 'Turbo Cells'
PCMag editors select and review products independently. If you buy through affiliate links, we may earn commissions, which help support our testing. As Intel prepares to manufacture chips with its 18A process, the company is previewing its next chip node, 14A, which will feature a mysterious "turbo cell" technology meant to boost CPU and even GPU speeds. First disclosed a year ago, Intel's 14A process promises to pack even more transistors on the silicon, improving the CPU density. On Tuesday, the company confirmed the 14A process will offer a 15% to 20% performance-per-watt increase over the 18A process. The 14A process will introduce a new 'turbo cell' technology designed to further increase the chip's speeds, 'including CPU maximum frequency and GPU critical paths,' Intel says. 'Turbo Cells allows designers to optimize a mix of more performant cells and more power-efficient cells within a design block, enabling a tailored balance between power, performance, and area for target applications,' Intel said in a statement, which was first reported by PCWorld. So far, Intel hasn't elaborated on the turbo cell feature. But the company discussed the 14A process at an Intel foundry event in San Jose as it tries to take on rival TSMC, the major chip maker for AMD, Apple, and Nvidia. Intel's 18A process is its most considerable effort yet to become a major semiconductor manufacturer after investing $90 billion over the last four years to build its foundry business. In addition to 18A, Intel says it's already talking with customers about using the 14A process. This includes distributing a Process Design Kit, or blueprint files, to help customers develop their chip designs for a specific process node. 'Multiple customers have expressed their intent to build test chips' on 14A, according to Intel. During Tuesday's event, Intel SVP for foundry services, Kevin O'Buckley, went out of his way to say that Intel is focused on becoming an "AI services company" at a time when AI chip demand has skyrocketed. He then showed a 3D image of what appeared to be an Nvidia-like enterprise-grade GPU packed with high-speed memory. Executives also emphasized that Intel has been listening to customer feedback to make the company's chip technology follow a "predictable 2-year cycle," and easy to plan around. Intel's roadmap adds that the 14A process will arrive in 2027, alongside a '14A-E' node developed to contain some additional 'feature extensions.' Along with the turbo cell technology, 14A chips will feature Intel's second-generation 'RibbonFET' and backside power delivery system to further boost performance. In the meantime, Intel plans to use its 18A chip node to develop semiconductors not only for third-party customers but also for its own business. This includes Intel's upcoming 'Panther Lake' laptop-focused CPUs, which are scheduled to arrive in the second half of this year. The company is also developing another node, called 18A-P, which will arrive next year. Intel says it's been 'designed to deliver enhanced performance to a broader set of foundry customers,' suggesting it can be used for chips outside general CPU computing.
Yahoo
22-04-2025
- Business
- Yahoo
Intel details next-gen 18A fab tech: significantly more performance, lower power, higher density
When you buy through links on our articles, Future and its syndication partners may earn a commission. Intel is set to detail (PDF) the advantages of its 18A manufacturing technology (1.8nm-class) compared to its Intel 3 fabrication process at the upcoming VLSI Symposium 2025. As expected, the new production node will offer substantial benefits across power, performance, and area (PPA) metrics, thus providing tangible advantages both for client and data center products. Intel claims that its 18A fabrication process delivers 25% more performance at the same voltage (1.1V) and complexity, as well as 36% lower power at the same frequency and voltage of 1.1V for a standard Arm core sub-block compared to the same block fabricated on Intel 3 process technology. At a lower voltage (0.75V), Intel 18A provides 18% higher performance and 38% lower power. In addition, 18A consistently achieves 0.72X area scaling compared to Intel 3. Intel's 18A manufacturing technology is the company's first node to rely on gate-all-around (GAA) RibbonFET transistors and feature PowerVia backside power delivery network (BSPDN), two features that enable major PPA advantages. The standard cell layout comparison highlights the significant physical scaling achieved by Intel 18A over Intel 3 in both High-Performance (HP) and High-Density (HD) libraries. Intel 18A reduces cell heights from 240CH to 180CH in HP libraries and from 210CH to 160CH in HD libraries, which represents a ~25% reduction in vertical dimension. This tighter cell architecture allows for increased transistor density, contributing directly to improved area efficiency. The use of PowerVia BSPDN enables more efficient vertical routing by offloading power lines from the front side of ICs, freeing up space for signal routing and further compacting the layout. Additionally, refined gate, source/drain, and contact structures improve overall cell uniformity and integration density. These enhancements collectively enable Intel 18A to deliver better performance-per-area and energy efficiency, supporting more advanced and compact chip designs. Intel is reportedly on track to start high-volume manufacturing of compute chiplets for its codenamed Panther Lake processors for client PCs later this year and then chiplets for Clearwater Forest data center systems in early 2026. In addition, the company is on track to tape out the first third-party designs on 18A in mid-2025. Apparently, there is interest in developing third-party chips for Intel 18A. In addition to presenting a general paper describing its 18A technology, Intel plans to present a paper describing a PAM-4 transmitter implemented using 18A production node with a BSPDN that is co-authored by engineers from Intel, Alphawave Semi (a contract chip designer and IP provider), Apple, and Nvidia. This does not necessarily mean that Apple or Nvidia will use Intel's 18A for production silicon, but this at least means that they are interested in checking it out. Speaking of Apple and Nvidia, TSMC said that virtually all of its partners plan to adopt its N2 (2nm-class) process technology, so it is reasonable to expect this node to be more widely used than Intel's 18A. Nonetheless, for Intel it is crucial to show that it can develop a competitive node and ramp it to high volume, so 18A will play a vital role for the future of Intel's foundry business.
Yahoo
18-03-2025
- Business
- Yahoo
Intel Fabricates 18A Test Wafers in Arizona
We have another sign that Intel's 18A 1.8nm class process is making significant progress: The company is producing wafers at one of its Arizona fabs, which means fabs in both Oregon and Arizona are capable of producing chips with the 18A process. The news comes by way of @Mojo_flyin on X, who appears to have screenshotted a LinkedIn post by Intel's Pankaj Marria before it was removed. As Tom's Hardware points out, Marria's brief post appeared while news of Intel's new CEO, Lip-Bu Tan, was dominating headlines. It doesn't appear that the Arizona fab is ramping up to mass production just yet. But the test wafers suggest that Intel is on pace, or maybe even a bit ahead of schedule, for producing 1.8nm-class chips in the middle of this year. If Intel can prove wrong the rumors about it struggling to get Panther Lake CPUs (based on the 18A process) into devices in 2025, that would be a noteworthy achievement. 'Proud to be part of the Eagle Team, leading the way in bringing Intel 18A technology to life!' Marria wrote in the LinkedIn post. 'Our team was at the forefront of running the initial lots right here in Arizona, marking a key step in advancing cutting-edge semiconductor manufacturing.' Credit: Intel Marria included a photo of people celebrating in front of a sign that reads: 'The Eagle Has Landed.' It's not clear why the post was removed, but it could be a timing issue. Intel was focused on Lip-Bu Tan's arrival, so the powers that be could reasonably have decided to hold off on the news of the 18A milestone. After years of struggle and with competitors circling, Intel could be finding its footing. The 18A process stands to provide energy-efficient chips and could be big business for Intel—if customers are satisfied with the technology. Former Intel CEO Pat Gelsinger famously suggested (possibly in jest) that he was betting the future of the company on 18A. Although he departed and Lip-Bu Tan now leads Intel, 18A still stands to play a major role. Panther Lake CPUs will appear in mobile devices. They have advanced AI capabilities, LPDDR5X memory, and multiple efficiency and low-power-efficiency cores, in addition to performance cores. The focus on energy efficiency is crucial for mobile devices, but the chips should pack a punch, as well. They'll include RibbonFET gate-all-around (GAA) tech, which allows for better power efficiency and denser chips.
Yahoo
15-03-2025
- Business
- Yahoo
Intel reaches 'exciting milestone' for 18A 1.8nm-class wafers with first run at Arizona fab
When you buy through links on our articles, Future and its syndication partners may earn a commission. While the whole market was looking at the appointment of Lip-Bu Tan as Intel chief executive, there was another major development at the company this week: The first 18A (1.8nm-class) wafers are running around Intel's Arizona fab. Intel's Fab 52 and Fab 62 in Arizona are high-volume production facilities, so running 18A fabs there is a major milestone for the company. "Exciting Milestone for Intel 18A," wrote Pankaj Marria, an engineering manager at Intel, in a LinkedIn post that was eventually hidden but captured by @Mojo_flyin on X. "Proud to be part of the Eagle Team, leading the way in bringing Intel 18A technology to life! Our team was at the forefront of running the initial lots right here in Arizona, marking a key step in advancing cutting-edge semiconductor manufacturing." Up until recently, Intel processed wafers on its 18A production technology at its site near Hillsboro, Oregon, where new manufacturing processes are developed. While the company can volume produce chips in Oregon as well, porting this new fabrication process to a brand-new fab in Arizona is indeed a milestone for the company. For now, the company is running test wafers to ensure that the fabrication process transfer is a success, but eventually the fab will start running actual chips for commercial products. Intel is set to mass produce compute chiplets for its upcoming codenamed Panther Lake processors on 18A technology later this year. Eventually, Intel's 18A production node will be used to make Intel's Xeon 7 codenamed Clearwater Forest processor for datacenters. Intel pins a lot of hope on the upcoming 18A fabrication process. The manufacturing technology relies on gate-all-around RibbonFET transistors that promise to increase performance and cut down power consumption. It also features backside power delivery, which is meant to ensure steady power delivery to power-hungry processors and increase transistor density by decoupling signal and power wires within a chip. "This achievement is a testament to the hard work, innovation, and dedication of everyone involved. The Eagle has landed, and this is just the beginning! Developed and Made in America the world's smallest node," Marria added. Sign in to access your portfolio
